Integrated chip and data processing method

Patent metadata

Field	Value
Publication number	US-2022114111-A1
Application number	US-202117558431-A
Country	US
Kind code	A1
Filing date	Dec 21, 2021
Priority date	Jun 21, 2019
Publication date	Apr 14, 2022
Grant date	—

Abstract

An integrated chip and a data processing method are provided, to improve system security and service processing efficiency of a system. The integrated chip includes: an application processor, configured to write first data into an off-chip memory in a normal secure mode by using a storage controller, where an address of the first data in the off-chip memory is a first address; a security processor, configured to send a first read instruction to the storage controller in an enhanced secure mode, where the first read instruction is used to request to read the first data at the first address; and the storage controller, configured to control the security processor to read the first data from the off-chip memory.

First claim

What is claimed is:

1 . An integrated chip, comprising:
an application processor, configured to send, in a normal secure mode, first data to a storage controller to prompt the storage controller to write the first data into a first address of an off-chip memory; and a security processor, configured to send, in an enhanced secure mode, a first read instruction to the storage controller to prompt the storage controller to read the first data at the first address and to send the first data to the security processor.

2 . The integrated chip according to claim 1 wherein the security processor is further configured to: process the read first data in the enhanced secure mode, and send the processed data to the storage controller to write into the off-chip memory.

3 . The integrated chip according to claim 2 wherein the application processor is further configured to, in the normal secure mode, retrieve and read the processed data from the off-chip memory via the storage controller.

4 . The integrated chip according to claim 3 , wherein the application processor is further configured to:
send a second read instruction to the storage controller in the normal secure mode, prompt the storage controller to read the processed data and to send the processed data to the application processor.

5 . The integrated chip according to claim 3 , wherein the security processor is further configured to:
after writing the processed data into the off-chip memory via the storage controller, notify, in an interrupt manner, the application processor to read the processed data.

6 . The integrated chip according to claim 1 , wherein the application processor is further configured to:
after writing the first data into the off-chip memory via the storage controller, notify, in the interrupt manner, the security processor to read the first data.

7 . The integrated chip according to claim 1 , wherein before the storage controller reads the first data, the storage controller is further configured to:
determine that the first read instruction is authenticated.

8 . The integrated chip according to claim 7 , wherein the storage controller is further configured to:
determine that the first address belongs to a first storage area of the off-chip memory, wherein the first storage area is configured to allow a processor in the normal secure mode to perform a write or read operation and allow a processor in the enhanced secure mode to perform a read operation; and determine that the security processor is in the enhanced secure mode and the first read instruction is a read instruction.

9 . The integrated chip according to claim 3 , wherein the security processor is further configured to:
send, in the enhanced secure mode, a first write instruction to the storage controller to indicate the storage controller to write the processed data into a second address; and the storage controller is further configured to: determine that the first write instruction is authenticated; and write the processed data into the second address.

10 . The integrated chip according to claim 9 , wherein the storage controller is further configured to:
determine that the second address belongs to a second storage area of the off-chip memory, wherein the second storage area is configured to allow the processor in the enhanced secure mode to perform a write or read operation and allow the processor in the normal secure mode to perform a read operation; and determine that the security processor is in the enhanced secure mode.

11 . The integrated chip according to claim 3 , wherein the security processor is further configured to:
before processing the read first data, write second data into the off-chip memory in the enhanced secure mode by using the storage controller, wherein an address of the second data in the off-chip memory is a third address; and wherein the security processor is further configured to: send, in the enhanced secure mode, a third read instruction to the storage controller to request to read the second data at the third address; read the second data from the off-chip memory by using the storage controller; and compare the first data with the second data, and use a comparison result as the processed data.

12 . An integrated chip, comprising:
an interconnect bus comprising a first signal cable and a second signal cable, wherein the first signal cable is configured to transmit enhanced security indication information, and the second signal cable is configured to transmit normal security indication information; a security processor, configured to send a first read instruction to a storage controller in an enhanced secure mode by using the interconnect bus, wherein enhanced security indication information comprised in the first read instruction is transmitted by using the first signal cable; and an application processor, configured to send a second read instruction to the storage controller in a normal secure mode by using the interconnect bus, wherein normal security indication information comprised in the second read instruction is transmitted by using the second signal cable.

13 . The integrated chip according to claim 12 , further comprising:
the storage controller, configured to: when the enhanced security indication information comprised in the first read instruction is a first specified value, determine that the security processor is in the enhanced secure mode.

14 . The integrated chip according to claim 13 , wherein the storage controller is further configured to:
when the normal security indication information in the second read instruction is a second specified value, determine that the application processor is in the normal secure mode; or when the normal security indication information in the second read instruction is a third specified value, determine that the application processor is in a non-secure mode.

15 . A data processing method, comprising:
receiving, by a storage controller, a first read instruction sent by a security processor, wherein the first read instruction is used to request to read first data at a first address in an off-chip memory; determining, by the storage controller, that the first read instruction is authenticated; and reading, by the storage controller, the first data from the off-chip memory, and sending the first data to the security processor.

16 . The method according to claim 15 , wherein the determining, by the storage controller, that the first read instruction is authenticated comprises:
determining, by the storage controller by querying a local register, that the first address belongs to a first storage area of the off-chip memory, wherein the first storage area is configured to allow a processor in the normal secure mode to perform a write or read operation and allow a processor in the enhanced secure mode to perform a read operation; and determining, by the storage controller, that the security processor is in the enhanced secure mode and the first read instruction is a read instruction.

17 . The method according to claim 16 , wherein the determining, by the storage controller, that the security processor is in the enhanced secure mode comprises:
when enhanced security indication information in the first read instruction is a first specified value, determining, by the storage controller, that the security processor is in the enhanced secure mode.

18 . The method according to claim 16 , further comprising:
receiving, by the storage controller, first configuration information sent by the

Assignees

• Huawei Tech Co Ltd

Inventors

• Gao Changjian
• Liu Yu

Classifications

• G06F12/1441

  for a range · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/1458 Primary

  by checking the subject access rights · CPC title

• G06F3/0622

  in relation to access · CPC title