Techniques to expand system memory via use of available device memory

Patent metadata

Field	Value
Publication number	US-2022114086-A1
Application number	US-202117560007-A
Country	US
Kind code	A1
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Apr 14, 2022
Grant date	—

Abstract

Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.

First claim

What is claimed is:

1 . An apparatus comprising:
circuitry at a device coupled with a host device, the circuitry to:
partition a first portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload, the first portion of memory capacity having a device physical address (DPA) range;
report to the host device that the first portion of memory capacity of the memory having the DPA range is available for use as a portion of pooled system memory managed by the host device; and
receive an indication from the host device that the first portion of memory capacity of the memory having the DPA range has been identified for use as a first portion of pooled system memory.

2 . The apparatus of claim 1 , wherein a second portion of pooled system memory managed by the host device includes a physical memory address range for memory resident on or directly attached to the host device.

3 . The apparatus of claim 2 , wherein the host device directs non-paged memory allocations to the second portion of pooled system memory and prevents non-paged memory allocations to the first portion of pooled system memory.

4 . The apparatus of claim 2 , comprising the host device to cause a memory allocation mapped to physical memory addresses included in the first portion of pooled system memory to be given to an application hosted by the host device for the application to store data, wherein responsive to the application requesting a lock on the memory allocation, the host device is to cause the memory allocation to be remapped to physical memory addresses included in the second portion of pooled system memory and to cause data stored to the physical memory addresses include in the first portion to be copied to the physical memory addresses included in the second portion.

5 . The apparatus of claim 2 , further comprising the circuitry to:
monitor memory usage of the memory configured for use by the compute circuitry resident at the device to determine whether the first portion of memory capacity is needed for the compute circuitry to execute the workload; cause a request to be sent to the host device, the request to reclaim the first portion of memory capacity having the DPA range from being used as the first portion based on a determination that the first portion of memory capacity is needed; and remove, responsive to approval of the request, the partition of the first portion of memory capacity of the memory configured for use by the compute circuitry such that the compute circuitry is able to use all the memory capacity of the memory to execute the workload.

6 . The apparatus of claim 1 , comprising the device coupled with the host device via one or more Compute Express Link (CXL) transaction links including a CXL.io transaction link or a CXL.mem transaction link.

7 . The apparatus of claim 1 , the compute circuitry comprising a graphics processing unit, wherein the workload is a graphics processing workload.

8 . The apparatus of claim 1 , the compute circuitry comprising a field programmable gate array or an application specific integrated circuit, wherein the workload is an accelerator processing workload.

9 . A method comprising:
partitioning, at a device coupled with a host device, a first portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload, the first portion of memory capacity having a device physical address (DPA) range; reporting to the host device that the first portion of memory capacity of the memory having the DPA range is available for use as a portion of pooled system memory managed by the host device; and receiving an indication from the host device that the first portion of memory capacity of the memory having the DPA range has been identified for use as a first portion of pooled system memory.

10 . The method of claim 9 , wherein a second portion of pooled system memory managed by the host device includes a physical memory address range for memory resident on or directly attached to the host device.

11 . The method of claim 10 , wherein the host device directs non-paged memory allocations to the second portion of pooled system memory and prevents non-paged memory allocations to the first portion of pooled system memory.

12 . The method of claim 10 , comprising the host device to cause a memory allocation mapped to physical memory addresses included in the first portion of pooled system memory to be given to an application hosted by the host device for the application to store data, wherein responsive to the application requesting a lock on the memory allocation, the host device is to cause the memory allocation to be remapped to physical memory addresses included in the second portion of pooled system memory and to cause data stored to the physical memory addresses include in the first portion to be copied to the physical memory addresses included in the second portion.

13 . The method of claim 10 , further comprising:
monitoring memory usage of the memory configured for use by the compute circuitry resident at the device to determine whether the first portion of memory capacity is needed for the compute circuitry to execute the workload; requesting, to the host device, to reclaim the first portion of memory capacity having the DPA range from being used as the first portion based on a determination that the first portion of memory capacity is needed; and removing, responsive to approval of the request, the partition of the first portion of memory capacity of the memory configured for use by the compute circuitry such that the compute circuitry is able to use all the memory capacity of the memory to execute the workload.

14 . The method of claim 9 , comprising the device coupled with the host device via one or more Compute Express Link (CXL) transaction links including a CXL.io transaction link or a CXL.mem transaction link.

15 . The method of claim 9 , the compute circuitry comprising a graphics processing unit, wherein the workload is a graphics processing workload.

16 . At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, cause circuitry to:
partition, at a device coupled with a host device, a first portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload, the first portion of memory capacity having a device physical address (DPA) range; report to the host device that the first portion of memory capacity of the memory having the DPA range is available for use as a portion of pooled system memory managed by the host device; and receive an indication from the host device that the first portion of memory capacity of the memory having the DPA range has been identified for use as a first portion of pooled system memory.

17 . The least one non-transitory computer-readable storage medium of claim 16 , wherein a second portion of pooled system memory managed by the host device includes a physical memory address range for memory resident on or directly attached to the host device.

18 . The least one non-transitory computer-readable storage medium of claim 17 , wherein the host device directs non-paged memory allocations to the second portion of pooled system memory and prevents non-paged memory allocations to the first portion of pooled system memory.

19 . The least one non-transitory computer-readable storage medium of claim 17 , comprising the hos

Assignees

• Intel Corp

Inventors

• Clark Chace A
• Boyd James A
• Douglas Chet R
• Rudoff Andrew M
• Williams Dan J

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2209/508

  Monitor · CPC title

• G06F9/5022 Primary

  Mechanisms to release resources · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F12/023 Primary

  Free address space management · CPC title