Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2022102371-A1
Application number	US-202117211460-A
Country	US
Kind code	A1
Filing date	Mar 24, 2021
Priority date	Sep 25, 2020
Publication date	Mar 31, 2022
Grant date	—

Abstract

The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate; and a plurality of channel structures passing through the stack in a vertical direction, wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and wherein a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.

2 . The semiconductor memory device of claim 1 ., wherein at least one first gate electrode that is disposed at an uppermost portion of the plurality of gate electrodes corresponds to a first select transistor, and at least one second gate electrode that is disposed at a lowermost portion of the plurality of gate electrodes corresponds to a second select transistor.

3 . The semiconductor memory device of claim 2 , wherein the partial region of the core insulating layer is adjacent to the first gate electrode.

4 . The semiconductor memory device of claim 2 , wherein the partial region of the core insulating layer is adjacent to the second gate electrode.

5 . The semiconductor memory device of claim 2 , wherein the partial region of the core insulating layer is adjacent to the first gate electrode and the second gate electrode.

6 . The semiconductor memory device of claim 1 , wherein a dopant is injected into the partial region of the core insulating layer.

7 . The semiconductor memory device of claim 6 , wherein the dopant is carbon, fluorine, or both carbon and fluorine.

8 . The semiconductor memory device of claim 1 , wherein the partial region of the core insulating layer includes a gap.

9 . A semiconductor memory device comprising:
a stack with a plurality of interlayer insulating layers and gate electrodes alternately stacked on a substrate; and a plurality of channel structures passing through the stack in a vertical direction, wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, at least one first gate electrode that is disposed at an uppermost portion of the gate electrodes corresponds to a drain select transistor, at least one second gate electrode that is disposed at a lowermost portion of the gate electrodes corresponds to a source select transistor, and remaining gate electrodes among the electrodes correspond to the memory cells, and a partial region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode has a dielectric constant that is lower than a dielectric constant of another region that is adjacent to the remaining gate electrodes.

10 . The semiconductor memory device of claim 9 , wherein a dopant is injected into the partial region of the core insulating layer.

11 . The semiconductor memory device of claim 10 , wherein the dopant is carbon, fluorine, or both carbon and fluorine.

12 . The semiconductor memory device of claim 9 , wherein a gap is formed in the partial region of the core insulating layer.

13 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate; forming a plurality of holes that pass through the stack in a vertical direction; sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalk of each of the plurality of holes; forming a core insulating layer on a sidewall of the channel layer to fill center regions of the plurality of holes; and injecting a dopant into a partial region so that a dielectric constant of the partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.

14 . The method of claim 13 , further comprising:
removing the plurality of sacrificial layers; and forming gate electrodes in a space from which the sacrificial layers are removed.

15 . The method of claim 14 , wherein at least one first gate electrode that is disposed at a lowermost portion of the gate electrodes and at least one second gate electrode that is disposed at an uppermost portion of the gate electrodes correspond to a select transistor.

16 . The method of claim 15 , wherein the partial region is a region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode.

17 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate; forming a plurality of holes that pass through the stack in a vertical direction; sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalls of each of the plurality of holes; and forming a core insulating layer on a sidewall of the channel layer to fill a center region of the plurality of holes, wherein forming the core insulating layer comprises forming a gap in a partial region of the core insulating layer.

18 . The method of claim 17 , further comprising:
removing the plurality of sacrificial layers; and forming gate electrodes in a space from which the sacrificial layers are removed.

19 . The method of claim 18 , wherein at least one first gate electrode that is disposed at a lowermost portion of the gate electrodes and at least one second gate electrode that is disposed at an uppermost portion of the gate electrodes correspond to a select transistor.

20 . The method of claim 19 , wherein the partial region is a region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode.

Assignees

• Sk Hynix Inc

Inventors

• Yun dae hwan
• Choi Gil Bok

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H01L27/1157

  Electricity · mapped topic