Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022085797-A1
Application number	US-202117449079-A
Country	US
Kind code	A1
Filing date	Sep 27, 2021
Priority date	Jun 13, 2019
Publication date	Mar 17, 2022
Grant date	—

Abstract

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first scan input NAND gate configured to perform a NAND operation on a first scan input signal and a first scan enable signal to output a first output signal; a second scan input NAND gate configured to perform a NAND operation on an inverted first scan enable signal and a first data signal to output a second output signal; a first scan input circuit including a third scan input NAND gate configured to perform a NAND operation on the first output signal and the second output signal to output a third output signal; a first master latch configured to latch the third output signal to output a fourth output signal; a first slave latch configured to latch the fourth output signal to output a fifth output signal; a first inverter configured to invert the fifth output signal to output a first final output signal; a first scan output circuit configured to receive a signal output from the first slave latch and a first external signal to output a first scan output signal; a fourth scan input NAND gate configured to perform a NAND operation on an inverted second scan enable signal and a second data signal to output a sixth output signal; a second scan input circuit including a fifth scan input NAND gate configured to perform a NAND operation on the first scan output signal and the sixth output signal to output a seventh output signal; a second master latch configured to latch the seventh output signal to output an eighth output signal; a second slave latch configured to latch the eighth output signal to output a ninth output signal; a second inverter configured to invert the ninth output signal to output a second final output signal; and a second scan output circuit configured to receive a signal output from the second slave latch and a second external signal to output a second scan output signal.

2 . The semiconductor device of claim 1 , wherein:
the signal output from the first slave latch includes the fifth output signal; and the first scan output circuit includes: a first scan output inverter configured to invert the fifth output signal to output a tenth output signal; and a second scan output inverter configured to invert the tenth output signal to output an eleventh output signal, wherein ground terminals of the first scan output inverter and the second scan output inverter receive an inverted first scan enable signal.

3 . The semiconductor device of claim 2 , wherein:
the first scan output circuit includes a scan output NAND gate configured to receive the external signal and the eleventh output signal and perform a logical operation on the external signal and the eleventh output signal; and the external signal includes the first scan enable signal.

4 . The semiconductor device of claim 1 , wherein:
the first slave latch includes a third inverter; the third inverter inverts the fourth output signal to output a tenth output signal; and the external signal includes an inverted first scan enable signal.

5 . The semiconductor device of claim 4 , wherein the first scan output circuit includes:
a first scan output inverter configured to invert the tenth output signal to output an eleventh output signal; and a second scan output inverter configured to invert the eleventh output signal to output a twelfth output signal,
wherein ground terminals of the first scan output inverter and the second scan output inverter receive an inverted first scan enable signal.

6 . A semiconductor device comprising:
a first scan input circuit configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal; a first master latch configured to latch the first select signal to output a first output signal; a first slave latch configured to latch the first output signal to output a second output signal, wherein the first slave latch includes a first reset NOR gate, and the reset NOR gate configured to perform NOR operation with a reset signal and the second output signal and output a third output signal; a second scan input circuit configured to receive the third output signal, a second data signal, and the scan enable signal and select any one of the second data signal and the third output signal in response to the scan enable signal to output a second select signal; a second master latch configured to latch the second select signal to output a fourth output signal; a second slave latch configured to latch the fourth select signal to output a fifth output signal; and a scan output circuit configured to receive a signal output from the second slave latch and an external signal to output a first scan output signal.

7 . The semiconductor device of claim 6 , wherein:
the scan output circuit includes: a first scan output inverter configured to invert the fifth output signal to output a sixth output signal; and a second scan output inverter configured to invert the sixth output signal to output a seventh output signal, wherein ground terminals of the first scan output inverter and the second scan output inverter receive an inverted scan enable signal.

8 . The semiconductor device of claim 7 , wherein:
the scan output circuit includes a scan output NAND gate configured to receive the external signal and the seventh output signal and perform a logic operation on the external signal and the seventh output signal to output a scan output signal; and the external signal includes the scan enable signal.

9 . The semiconductor device of claim 7 , wherein:
the scan output circuit includes a scan output NOR gate configured to receive the external signal and the seventh output signal and perform a logic operation on the external signal and the seventh output signal to output a scan output signal; and
the external signal includes the inverted scan enable signal.

10 . A semiconductor device comprising:
a first scan input NAND gate configured to perform a NAND operation on a first scan input signal and a first scan enable signal to output a first output signal; a second scan input NAND gate configured to perform a NAND operation on an inverted first scan enable signal and a first data signal to output a second output signal; a first scan input circuit including a third scan input NAND gate configured to perform a NAND operation on the first output signal and the second output signal to output a third output signal; a first master latch configured to latch the third output signal to output a fourth output signal; a first slave latch configured to latch the fourth output signal to output a fifth output signal; a first inverter configured to invert the fifth output signal to output a first final output signal; a first scan output circuit configured to receive a signal output from the first slave latch and a first external signal to output a first scan output signal; a fourth scan input NAND gate configured to perform a NAND operation on an inverted second scan enable signal and a second data signal to output a sixth output signal; a second scan input circuit including a fifth scan input NAND gate configured to perform a NAND operation on an inverted first scan output signal and the sixth output signal to output a seventh output signal; a second master latch configured to latch the seventh output signal to output an eighth output signal; a second slave latch configured to latch the eighth output signal to output a ninth output signal; a second inverter configured to invert the ninth output signal to output a second final output signal; and a sec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim San Ha
• Shin Taek Kyun
• Kim Min Su

Classifications

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G01R31/318371

  Methodologies therefor, e.g. algorithms, procedures · CPC title