Semiconductor devices

Patent metadata

Field	Value
Publication number	US-2022069101-A1
Application number	US-202117196321-A
Country	US
Kind code	A1
Filing date	Mar 9, 2021
Priority date	Aug 31, 2020
Publication date	Mar 3, 2022
Grant date	—

Abstract

A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including:
a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and
a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate,
wherein: an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

2 . The semiconductor device as claimed in claim 1 , further comprising a capping layer on the polishing stop pattern,
wherein an upper surface of the capping layer is substantially coplanar with the upper surface of the central portion of the first portion of the polishing stop pattern or the upper surface of the second portion of the polishing stop pattern.

3 . The semiconductor device as claimed in claim 2 , wherein:
the substrate includes a first region and a second region, the gate structure is a first gate structure on the first region of the substrate, the gate spacer, the polishing stop pattern, and the capping layer are a first gate spacer, a first polishing stop pattern and a first capping layer, respectively, the semiconductor device further comprises: a second gate structure on the second region of the substrate; a second gate spacer on a sidewall of the second gate structure; a second polishing stop pattern on the second gate structure and the second gate spacer; and a second capping layer on the second polishing stop pattern, the second polishing stop pattern including:
a first portion covering an upper surface of the second gate structure and an upper surface of the second gate spacer; and
a second portion extending from the first portion in the vertical direction, and
an upper surface of the second capping layer is substantially coplanar with an upper surface of the second portion of the second polishing stop pattern.

4 . The semiconductor device as claimed in claim 1 , wherein an upper surface of a central portion of the gate structure contacting the central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the gate structure.

5 . The semiconductor device as claimed in claim 4 , wherein:
the gate structure includes:
a second gate electrode;
a first gate electrode covering a sidewall and a lower surface of the second gate electrode;
a gate barrier covering a sidewall and a lower surface of the first gate electrode; and
a gate insulation pattern covering a sidewall and a lower surface of the gate barrier, and
an upper surface of the second gate electrode is higher than an uppermost surface of each of the first gate electrode, the gate barrier, and the gate insulation pattern.

6 . The semiconductor device as claimed in claim 5 , wherein:
the second gate electrode includes tungsten, the first gate electrode includes titanium aluminum carbide, and the gate barrier includes titanium nitride.

7 . The semiconductor device as claimed in claim 1 , wherein the polishing stop pattern includes silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or an amorphous carbon layer.

8 . The semiconductor device as claimed in claim 1 , wherein the polishing stop pattern includes polysilicon or boronitride.

9 . The semiconductor device as claimed in claim 1 , wherein the polishing stop pattern includes a transition metal.

10 . The semiconductor device as claimed in claim 1 , further comprising:
a source/drain layer on a portion of the substrate adjacent to the gate structure; a first insulating interlayer on the source/drain layer, the first insulating interlayer covering a sidewall of the gate spacer and a sidewall of the polishing stop pattern; and a first contact plug extending through the first insulating interlayer to contact an upper surface of the source/drain layer, wherein an upper surface of the first contact plug is substantially coplanar with the upper surface of the central portion of the first portion of the polishing stop pattern or the upper surface of the second portion of the polishing stop pattern.

11 . The semiconductor device as claimed in claim 10 , further comprising an etch stop layer commonly on the polishing stop pattern, the first insulating interlayer, and the first contact plug.

12 . The semiconductor device as claimed in claim 11 , further comprising:
a second contact plug extending through the etch stop layer to contact an upper surface of the first contact plug; and a third contact plug extending through the etch stop layer and the polishing stop pattern to contact an upper surface of the gate structure.

13 . A semiconductor device, comprising:
a substrate; channels spaced apart from each other on the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the channels extending in a first direction substantially parallel to the upper surface of the substrate; a gate structure extending on the substrate in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the gate structure covering lower and upper surfaces and opposite sidewalls in the second direction of the channels; a gate spacer on an upper sidewall of the gate structure; a polishing stop pattern on the gate structure and the gate spacer; a source/drain layer on a portion of the substrate adjacent to the gate structure, the source/drain layer being connected to each of opposite sidewalls in the first direction of the channels; a first insulating interlayer on the source/drain layer, the first insulating interlayer covering a sidewall of the gate spacer and a sidewall of the polishing stop pattern; and a first contact plug extending through the first insulating interlayer to contact an upper surface of the source/drain layer, an upper surface of the first contact plug being substantially coplanar with an upper surface of the polishing stop pattern.

14 . The semiconductor device as claimed in claim 13 , wherein the polishing stop pattern includes silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or an amorphous carbon layer.

15 . The semiconductor device as claimed in claim 13 , further comprising:
an etch stop layer commonly on the polishing stop pattern, the first insulating interlayer, and the first contact plug; a second contact plug extending through the etch stop layer and contacting an upper surface of the first contact plug; and a third contact plug extending through the etch stop layer and the polishing stop pattern and contacting an upper surface of the gate structure.

16 . The semiconductor device as claimed in claim 13 , wherein:
the polishing stop pattern includes:
a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and
a second portion extending from the first portion in the vertical direction, and
an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Seunghoon
• Yoon Ilyoung
• Park Ilsu
• Bae Kiho
• Yoon Boun
• Lee Yooyong

Classifications

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0137

  the gate conductors being silicided · CPC title