Light-emitting diode driver and light-emitting diode driving device

Patent metadata

Field	Value
Publication number	US-2022039231-A1
Application number	US-202117388748-A
Country	US
Kind code	A1
Filing date	Jul 29, 2021
Priority date	Jul 29, 2020
Publication date	Feb 3, 2022
Grant date	—

Abstract

A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.

First claim

What is claimed is:

1 . A light-emitting diode LED driver, comprising:
a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal; and an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, wherein the data signal is encoded in a first encoding format, the encoded data signal is encoded in a second encoding format, and the first encoding format and the second encoding format are different encoding formats.

2 . The LED driver according to claim 1 , wherein at least one of the first encoding format and the second encoding format is one of a Manchester encoding format and a four-level pulse amplitude modulation (PAM4) encoding format.

3 . The LED driver according to claim 2 , wherein when the first encoding format is the Manchester encoding format, the decoding circuit comprises:
a first delay circuit that delays a timing of the received data signal to generate a first recovered data signal; a first sampling circuit that samples the received data signal to generate a second recovered data signal; and a first logic operation circuit that performs a logic operation on the first recovered data signal and the second recovered data signal to generate the decoded display data and the recovered clock signal; wherein the first sampling circuit samples the received data signal by using the recovered clock signal.

4 . The LED driver according to claim 3 , wherein the first delay circuit delays the received data signal by 1/4 period to generate the first recovered data signal.

5 . The LED driver according to claim 4 , wherein the first sampling circuit comprises:
a second delay circuit that receives the recovered clock signal generated by the first logic operation circuit, and delays the recovered clock signal by 1/2 period to generate a sampling clock signal; and a first register that samples the received data signal by using the sampling clock signal to generate the second recovered data signal.

6 . The LED driver according to claim 5 , wherein the first logic operation circuit comprises:
a first logic gate circuit that performs an exclusive OR operation on the first recovered data signal and the second recovered data signal to generate the recovered clock signal; and a second logic gate circuit that inverts the second recovered data signal to generate the decoded display data.

7 . The LED driver according to claim 2 , wherein when the second encoding format is the Manchester encoding format, the encoding circuit comprises:
a first data conversion circuit that converts the decoded display data by using a first clock signal obtained from the recovered clock signal to generate first converted data; a second sampling circuit that samples the first converted data to generate second converted data; and a second logic operation circuit that performs a logic operation on the second converted data and a second clock signal obtained from the recovered clock signal to generate the encoded data signal.

8 . The LED driver according to claim 7 , wherein the first data conversion circuit comprises:
a first frequency dividing circuit that divides the received recovered clock signal to generate a second clock signal, and outputs the second clock signal as a first clock signal; a second register that samples the decoded display data by using the first clock signal, and outputs first sampled data; a third register that samples the decoded display data by using a signal that is inverted from the first clock signal, and outputs second sampled data; and a data selector that receives the first sampled data and the second sampled data, and selects, based on a level of the first clock signal, one of the first sampled data and the second sampled data as the first converted data and outputs it to the second sampling circuit.

9 . The LED driver according to claim 7 , wherein the first data conversion circuit comprises:
a first frequency dividing circuit that divides the received recovered clock signal to generate a second clock signal; a phase delay circuit that performs phase delay on the second clock signal output by the first frequency dividing circuit, and outputs the phase-delayed second clock signal as the first clock signal; a second register that samples the decoded display data by using the first clock signal, and outputs first sampled data; a third register that samples the decoded display data by using a signal that is inverted from the first clock signal, and outputs second sampled data; and a data selector that receives the first sampled data and the second sampled data, and selects, based on a level of the first clock signal, one of the first sampled data and the second sampled data as the first converted data and outputs it to the second sampling circuit.

10 . The LED driver according to claim 7 , wherein the second sampling circuit comprises:
a fourth register that samples the first converted data by using a signal that is inverted from the recovered clock signal, and outputs the second converted data.

11 . The LED driver according to claim 8 , wherein the second logic operation circuit comprises:
a third logic gate circuit that performs an exclusive OR operation on the second clock signal output by the first frequency dividing circuit and the second converted data to generate the encoded data signal.

12 . The LED driver according to claim 9 , wherein the second logic operation circuit comprises:
a third logic gate circuit that performs an exclusive OR operation on the second clock signal output by the first frequency dividing circuit and the second converted data to generate the encoded data signal.

13 . The LED driver according to claim 2 , wherein when the first encoding format is the PAM4 encoding format, the decoding circuit comprises:
a preprocessing circuit that preprocesses the received data signal and outputs a preprocessed data signal; a comparator circuit that compares the preprocessed data signal with corresponding threshold signals to generate a corresponding bit thermometer code; a PAM4 decoder that decodes the bit thermometer code and outputs a decoded data signal.

14 . The LED driver of claim 13 , wherein the comparator circuit comprises:
a first comparator, a second comparator and a third comparator, wherein the first, second and third comparators set different threshold signals, and compare the preprocessed data signal with the different threshold signals, respectively, to generate corresponding bit thermometer codes.

15 . The LED driver according to claim 14 , wherein the decoding circuit further comprises a clock recovery circuit and a second data conversion circuit, wherein,
the clock recovery circuit receives a bit thermometer code output from one of the first, second and third comparators, extracts the recovered clock signal therefrom and outputs it to the second data conversion circuit; the second data conversion circuit converts the decoded data signal output by the PAM4 decoder by using the recovered clock signal to generate the decoded display data in a 2-tuple representation form.

16 . The LED driver of claim 15 , wherein the second data conversion circuit comprises:
a fifth register and a sixth register that sample the decoded data signal output by the PAM4 decoder by using the recovered clock signal, to output third sampled data and fourth sampled data respectively as the decoded display data in the 2-tuple representation form

Assignees

• Novatek Microelectronics Corp

Inventors

• Yeh Che-Wei
• Liang Keko-Chun
• Fang Yong-Ren
• Liu Yi-Chuan

Classifications

• H05B45/30

  Driver circuits · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H05B45/33 Primary

  Pulse-amplitude modulation [PAM] · CPC title