Method and apparatus for performing on-system phase-locked loop management in memory device

Patent metadata

Field	Value
Publication number	US-2022029630-A1
Application number	US-202117161552-A
Country	US
Kind code	A1
Filing date	Jan 28, 2021
Priority date	Jul 23, 2020
Publication date	Jan 27, 2022
Grant date	—

Abstract

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

First claim

What is claimed is:

1 . A method for performing on-system phase-locked loop (PLL) management in a memory device, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the method comprising:
utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit, wherein the transmission interface circuit comprises a physical layer (PHY) circuit, and the PHY circuit comprises the PLL, a trimming control circuit and the register circuit, wherein a voltage controlled oscillator (VCO) in the PLL is implemented with a voltage controlled crystal oscillator (VCXO), and the trimming control circuit is arranged to perform trimming control on the PLL, for supporting optimization of the PLL that uses the VCXO, wherein the optimization of the PLL comprises parameter adjustment of the PLL; utilizing the trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of the VCO, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage; and during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management of the memory device.

2 . The method of claim 1 , wherein the memory controller intermittently performs the parameter adjustment of the PLL and accesses the NV memory 120 in response to one or more host commands of the host device.

3 . The method of claim 1 , wherein the memory controller optimizes the control voltage with aid of an optimization working flow regarding the control voltage of the VCO; and
operations of the optimization working flow comprise: determining whether the memory device is in a power-up phase or an adapt equalization phase to generate a first determination result; in response to the first determination result indicating that the memory device is in the power-up phase or the adapt equalization phase, according to at least one predetermined rule, determining whether the parameter adjustment of the PLL is needed to generate a second determination result; in response to the second determination result indicating that the parameter adjustment of the PLL is needed, triggering the parameter adjustment of the PLL with a trim-enable parameter among the multiple control parameters; generating and storing the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL; and after completion of the parameter adjustment of the PLL, controlling the memory device to enter an idle state of the memory device and stay in the idle state until any event occurs.

4 . The method of claim 3 , wherein the any event represents one of multiple predetermined events, and the multiple predetermined events comprise a speed mode change and any host command received from the host device.

5 . The method of claim 3 , wherein in a first case that the any event represents a write command from the host device, the memory controller stores data into the NV memory for the host device in response to the write command from the host device, and controls the memory device to enter the idle state again after completing processing corresponding to the write command, wherein the processing corresponding to the write command comprises writing the data into the NV memory.

6 . The method of claim 5 , wherein in a second case that the any event represents a read command from the host device, the memory controller reads the stored data from the NV memory in response to the read command from the host device, and provides the host device with said stored data read from the NV memory, and controls the memory device to enter the idle state again after completing processing corresponding to the read command, wherein the processing corresponding to the read command comprises reading the stored data and providing the host device with said stored data.

7 . The method of claim 3 , wherein in a second case that the any event represents a read command from the host device, the memory controller reads stored data from the NV memory in response to the read command from the host device, and provides the host device with said stored data read from the NV memory, and controls the memory device to enter the idle state again after completing processing corresponding to the read command, wherein the processing corresponding to the read command comprises reading the stored data and providing the host device with said stored data.

8 . A memory device, comprising:
a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element; and a controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the controller comprises:
a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller; and
a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device, wherein the transmission interface circuit comprises:
a physical layer (PHY) circuit, comprising:
a phase-locked loop (PLL), wherein a voltage controlled oscillator (VCO) in the PLL is implemented with a voltage controlled crystal oscillator (VCXO);
a trimming control circuit, arranged to perform trimming control on the PLL, for supporting optimization of the PLL that uses the VCXO, wherein the optimization of the PLL comprises parameter adjustment of the PLL; and
a register circuit, arranged to store multiple parameters of the PLL, and store multiple processing results of the parameter adjustment of the PLL, wherein the multiple parameters comprise multiple control parameters;

wherein:
the controller utilizes the processing circuit to set the multiple control parameters, for controlling the parameter adjustment of the PLL;
the controller utilizes the trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of the VCO, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage; and
during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, the controller utilizes the trimming control circuit to generate and store the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving on-system PLL management of the memory device.

9 . An electronic device comprising the memory device of claim 8 , and further comprising:
a host device, coupled to the memory device

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title