Charge sensing device with readout of signal by detecting a change of capacitance of combined gate and quantum capacitance compared to a reference capacitance

Patent metadata

Field	Value
Publication number	US-2022014699-A1
Application number	US-202017427507-A
Country	US
Kind code	A1
Filing date	Jan 31, 2020
Priority date	Jan 31, 2019
Publication date	Jan 13, 2022
Grant date	—

Abstract

The present invention relates to a system comprising an electronic apparatus which comprises: —an electronic device comprising: —a gate electrode structure (G, BE); —a dielectric (D) arranged over the gate electrode (G, BE); and —a charge sensing structure (CE) with a 2-dimensional charge sensing layer to provide a gate capacitance (Cg) between the charge sensing structure (CE) and the gate electrode structure (G, BE) and a quantum capacitance (Cq) resulting in a total capacitance (Ctot); —a read-out circuit configured so that when the total capacitance (Ctot) changes due to a change in the quantum capacitance (Cq), an imbalance between the total capacitance (Ctot) and the reference capacitance (Cf) results in a change on the output voltage (Vo) that is amplified to provide the read-out signal (So). The present invention also relates to an electronic apparatus like the one of the system of the present invention.

First claim

1 . A system comprising an electronic apparatus, wherein the electronic apparatus comprises:
an electronic device comprising:
a gate electrode structure;
a dielectric structure arranged over said gate electrode structure; and
a charge sensing structure comprising at least one 2-dimensional charge sensing layer configured to sense electrical charges and/or electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure to provide a gate capacitance between the charge sensing structure and the gate electrode structure; wherein said charge sensing structure shows a quantum capacitance in series with said gate capacitance resulting in a total capacitance between the charge sensing structure and the gate electrode structure; and
a read-out circuit electrically connected to the charge sensing structure or to the gate electrode structure, to detect an output voltage that is representative of said sensed electrical charges stored in said total capacitance and provide a read-out signal based on the detected output voltage;
wherein said read-out circuit comprises:
an amplifier with a first input electrically connected to the charge sensing structure or to the gate electrode structure to detect said output voltage and provide, at an output of the amplifier, said read-out signal;
a reference capacitor that has a magnitude equal to or differing at maximum a 50% with respect to said total capacitance when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure, wherein said reference capacitor has a first plate electrically connected to said first input of the amplifier; and
a mechanism configured and arranged to select and apply a control voltage to the one of said gate electrode structure and said charge sensing structure which is not electrically connected to the first input of the amplifier; wherein said control voltage is selected such that the fermi level of the charge sensing structure is tuned to the most sensitive point;

so that when said total capacitance changes due to a change in the quantum capacitance caused by an electrical charge or electrical charge carrier density induced on the charge sensing structure, an imbalance between the total capacitance and the reference capacitance results in a change on the output voltage on the first input of the amplifier that is amplified to provide the read-out signal.

2 . The system of claim 1 , wherein the read-out circuit further comprises a first offset correction mechanism comprising said mechanism, which are configured and arranged to select and apply a first reference voltage to a second plate of the reference capacitor, so that the output voltage on the first input of the amplifier is zero when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure.

3 . The system of claim 1 , wherein said mechanism comprises at least one voltage source that generates at least said control voltage.

4 . The system of claim 1 , wherein said mechanism comprises a control unit configured and arranged to select and apply at least said control voltage.

5 . The system of claim 4 , wherein said control voltage is a DC voltage, an AC voltage, or a combination of DC and AC voltages, and wherein the control unit is configured to select the properties of said control voltage, at least regarding its magnitude.

6 . The system of claim 1 , wherein said read-out circuit further comprises a second offset correction mechanism comprising said mechanism, which is configured and arranged to select and apply to a second input of the amplifier a second reference voltage with a magnitude equal or substantially equal to the output voltage when the charge sensitivity structure is set to its most sensitivity point and there is no electrical charge or electrical charge carrier density induced by the external physical quantity.

7 . The system of claim 4 , wherein said read-out circuit further comprises a second offset correction mechanism comprising said mechanism, which are configured and arranged to select and apply to a second input of the amplifier a second reference voltage with a magnitude equal or substantially equal to the output voltage when the charge sensitivity structure is set to its most sensitivity point and there is no electrical charge or electrical charge carrier density induced by the external physical quantity, and wherein said control unit is also configured and arranged to select and apply said second reference voltage.

8 . The system of claim 1 , wherein said read-out circuitry further comprises a reset circuit to discharge the total capacitance.

9 . The system according to claim 1 , wherein the electronic device further comprises a sensitizing or functionalizing structure arranged over said charge sensing structure, wherein said sensitizing or functionalizing structure is configured to induce said electrical charges and/or modify the electrical charge carrier density therein induced by said external physical quantity, wherein the sensitizing or functionalizing structure only sensitive to said external physical quantity.

10 . The system of claim 1 , wherein said reference capacitor is a separate component, with respect to the electronic device.

11 . The system of claim 9 , wherein said reference capacitor is implemented by the electronic device, with said first plate constituted by said charge sensing structure, a dielectric structure constituted by said sensitizing or functionalizing structure, and said second plate constituted by a top electrode structure arranged over said sensitizing or functionalizing structure.

12 . The system of claim 1 , wherein the electronic device and at least part of the read-out circuitry are CMOS-implemented.

13 . The system of claim 9 , wherein said sensitizing or functionalizing structure is a photoactive structure configured and arranged to, upon illumination, generate electron-hole pairs which, due to a field created by either a Schottky junction between the charge sensing structure and the photoactive structure or a top electrode structure on top of the photoactive structure or an interlayer between the charge sensing structure and the photoactive structure, are separated and either the electrons or holes gets transported, as said induced electrical charge carriers, to the charge sensing structure.

14 . The system according to claim 13 , implementing an image sensor comprising an array of pixels, wherein the electronic apparatus comprises a plurality of said electronic devices each constituting one pixel of said array of pixels.

15 . An electronic apparatus, comprising:
an electronic device comprising:
a gate electrode structure;
a dielectric structure arranged over said gate electrode structure; and
a charge sensing structure comprising at least one 2-dimensional charge sensing layer configured to sense electrical charges and/or electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure to provide a gate capacitance between the charge sensing structure and the gate electrode structure; wherein said charge sensing structure shows a quantum capacitance in series with said gate capacitance between the charge sensing structure and the gate electrode structure; and
a read-out circuit electrically connected to the charge sensing structure or to the gate electrode structure, to detect an output voltage that is representative of said sensed electrical charges stored in said tota

Assignees

• Fundacio Inst De Ciencies Fotòniques
• Inst Catalana Recerca Estudis Avancats

Inventors

• Goossens Stijn
• Koppens Frank
• Konstantatos Gerasimos

Classifications

• G01R27/2605 Primary

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F30/282

  Insulated-gate field-effect transistors [IGFET], e.g. MISFET [metal-insulator-semiconductor field-effect transistor] phototransistors · CPC title

• H10F30/227 Primary

  the potential barrier being a Schottky barrier · CPC title