Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Patent metadata

Field	Value
Publication number	US-2022013638-A1
Application number	US-202117191778-A
Country	US
Kind code	A1
Filing date	Mar 4, 2021
Priority date	Jul 9, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a silicon carbide layer having a first face and a second face opposite to the first face, the first face being parallel to a first direction and a second direction orthogonal to the first direction, the silicon carbide layer including a first trench located on a side of the first face and extending in the first direction, a second trench located on a side of the first face and located in the second direction with respect to the first trench, a third trench located on a side of the first face, the third trench located in the second direction with respect to the first trench, the third trench located in the first direction with respect to the second trench, a first silicon carbide region of n type, a second silicon carbide region of p type located between the first silicon carbide region and the first face, a third silicon carbide region of n type located between the second silicon carbide region and the first face, a fourth silicon carbide region of p type located between the first silicon carbide region and the second trench, a fifth silicon carbide region of p type located between the first silicon carbide region and the third trench, and a sixth silicon carbide region of p type located between the second trench and the third trench, the sixth silicon carbide region having a depth smaller than a depth of the second trench, the sixth silicon carbide region having a p type impurity concentration higher than a p type impurity concentration of the second silicon carbide region; a gate electrode located in the first trench; a gate insulating layer located between the gate electrode and the silicon carbide layer; a first electrode located on a side of the first face of the silicon carbide layer, a part of the first electrode located in the second trench, the part of the first electrode being in contact with the fourth silicon carbide region on a bottom face of the second trench, the first electrode being in contact with the sixth silicon carbide region; and a second electrode located on a side of the second face of the silicon carbide layer, wherein a p type impurity concentration of a portion of the sixth silicon carbide region in contact with the first electrode is higher than a p type impurity concentration of a portion of the fourth silicon carbide region at the bottom face.

2 . The semiconductor device according to claim 1 , wherein a depth of the sixth silicon carbide region is smaller than a depth of the second silicon carbide region.

3 . The semiconductor device according to claim 1 , wherein the sixth silicon carbide region and the first electrode are in contact with each other on the first face.

4 . The semiconductor device according to claim 1 , wherein
the silicon carbide layer further including a fourth trench shallower than the second trench located between the second trench and the third trench, another part of the first electrode is located in the fourth trench, and the another part of the first electrode is in contact with the sixth silicon carbide region on a bottom face of the fourth trench.

5 . The semiconductor device according to claim 4 , wherein the another part of the first electrode is in contact with the third silicon carbide region on a side face of the fourth trench.

6 . The semiconductor device according to claim 4 , wherein the another part of the first electrode is in contact with the sixth silicon carbide region on a side face of the fourth trench.

7 . The semiconductor device according to claim 1 , wherein a p type impurity concentration of a portion of the sixth silicon carbide region in contact with the first electrode is equal to or more than 1×10 19 cm −3 .

8 . The semiconductor device according to claim 1 , wherein a p type impurity concentration of a portion of the sixth silicon carbide region in contact with the first electrode is equal to or more than 10 times a p type impurity concentration of a portion of the fourth silicon carbide region at the bottom face.

9 . The semiconductor device according to claim 1 , wherein a length of the second trench in the first direction is larger than a length of the second trench in the second direction.

10 . The semiconductor device according to claim 1 , wherein the silicon carbide layer further including a p type seventh silicon carbide region located between the first silicon carbide region and the first trench.

11 . The semiconductor device according to claim 1 , wherein a part of the first silicon carbide region is located between the second trench and the third trench.

12 . The semiconductor device according to claim 11 , wherein the part of the first silicon carbide region is located between the fourth silicon carbide region and the fifth silicon carbide region.

13 . The semiconductor device according to claim 1 , wherein the fourth silicon carbide region and the fifth silicon carbide region are in contact with each other.

14 . The semiconductor device according to claim 1 , wherein
the first silicon carbide region includes a first region and a second region, the second region is located between the first region and the second silicon carbide region and between the first trench and the second trench, and an n type impurity concentration of the second region is higher than an n type impurity concentration of the first region.

15 . An inverter circuit comprising a semiconductor device according to claim 1 .

16 . A drive device comprising a semiconductor device according to claim 1 .

17 . A vehicle comprising a semiconductor device according to claim 1 .

18 . An elevator comprising a semiconductor device according to claim 1 .

Assignees

• Toshiba Kk

Inventors

• Tanaka Katsuhisa
• Kyogoku Shinya
• Iijima Ryosuke
• Kimoto Shinichi
• Harada Shinsuke

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title

• H10D84/144

  in antiparallel diode configurations · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title