Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022013636-A1
Application number	US-202117201109-A
Country	US
Kind code	A1
Filing date	Mar 15, 2021
Priority date	Jul 7, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A predetermined relational expression holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is the other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and τ, respectively.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, an IGBT region, a diode region, and a current sense region being provided along an in-plane direction in the semiconductor substrate, the semiconductor substrate including:
a base layer provided on a first main surface side being a side of the first main surface, in the IGBT region;
a collector layer provided on a second main surface side being a side of the second main surface, in the IGBT region;
an anode layer provided on the first main surface side in the diode region;
a cathode layer provided on the second main surface side in the diode region and adjacent to the collector layer in the in-plane direction;
a first semiconductor layer provided on the first main surface side in the current sense region and corresponding to the base layer or the anode layer; and
a second semiconductor layer provided on the second main surface side in the current sense region and corresponding to one of the collector layer and the cathode layer,
wherein
[Expression 1]
W >√{square root over (2 S +√{square root over ( D τ)}+ D τ)}

Expression 1 holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is an other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and τ, respectively.

2 . The semiconductor device according to claim 1 , wherein
the first distance is more than 486.3 μm when the second distance is less than 120 μm, the lifetime is less than 30 μsec, and the semiconductor device has a maximum rated temperature of 150° C.

3 . The semiconductor device according to claim 1 , wherein
the first distance is more than 436.8 μm when the second distance is less than 60 μm, the lifetime is less than 30 μsec, and the semiconductor device has a maximum rated temperature of 125° C.

4 . The semiconductor device according to claim 1 , wherein
the first distance is more than 550.9 μm when the second distance is less than 190 μm, the lifetime is less than 30 μsec, and the semiconductor device has a maximum rated temperature of 150° C.

Assignees

• Mitsubishi Electric Corp

Inventors

• Otsuka Kakeru
• Oki Hirofumi
• Sako Kohei

Classifications

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D84/141

  VDMOS having built-in components · CPC title

• H10D12/411

  Insulated-gate bipolar transistors [IGBT] · CPC title

• H10D12/01

  Manufacture or treatment · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title