Vertical power semiconductor device and manufacturing method

Patent metadata

Field	Value
Publication number	US-2022013625-A1
Application number	US-202117370179-A
Country	US
Kind code	A1
Filing date	Jul 8, 2021
Priority date	Jul 13, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body including a semiconductor substrate and a semiconductor layer on the semiconductor substrate. The semiconductor body has a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. A first part of the drift region is arranged in the semiconductor substrate. A second part of the drift region is arranged in the semiconductor layer. The vertical power semiconductor device further includes a field stop region arranged in the semiconductor substrate, wherein a doping concentration of the field stop region averaged along the vertical direction is larger than a doping concentration of the drift region averaged along the vertical direction.

First claim

What is claimed is:

1 . A vertical power semiconductor device, comprising:
a semiconductor body including a semiconductor substrate and a semiconductor layer on the semiconductor substrate, wherein the semiconductor body has a first main surface and a second main surface opposite to the first main surface along a vertical direction; a drift region in the semiconductor body, wherein a first part of the drift region is arranged in the semiconductor substrate, and a second part of the drift region is arranged in the semiconductor layer; a field stop region arranged in the semiconductor substrate, wherein a doping concentration of the field stop region averaged along the vertical direction is larger than a doping concentration of the drift region averaged along the vertical direction.

2 . The vertical power semiconductor device of claim 1 , wherein a vertical extension of the first part ranges from 10% to 90% of a vertical extension of the drift region.

3 . The vertical power semiconductor device of claim 1 , wherein a vertical extension of the drift region is configured to block voltages ranging from 1.5 kV to 10 kV.

4 . The vertical power semiconductor device of claim 1 , wherein the semiconductor substrate is a Czochralski (CZ) semiconductor substrate.

5 . The vertical power semiconductor device of claim 4 , wherein the CZ semiconductor substrate is a Magnetic Czochralski (MCZ) semiconductor substrate.

6 . The vertical power semiconductor device of claim 1 , wherein a doping concentration of the first part averaged along the vertical direction is larger than an average doping concentration of the second part averaged along the vertical direction.

7 . The vertical power semiconductor device of claim 1 , wherein a doping concentration of the second part averaged along the vertical direction ranges from 1×10 12 cm −3 to 1×10 13 cm −3 .

8 . The vertical power semiconductor device of claim 1 , wherein a doping concentration of the first part averaged along the vertical direction ranges from 1×10 13 cm −3 to 2×10 14 cm −3 .

9 . The vertical power semiconductor device of claim 1 , wherein a vertical distance between the field stop region and the second main surface along the vertical direction ranges from 0 μm to 30 μm.

10 . The vertical power semiconductor device of claim 1 , wherein an oxygen concentration in at least part of the semiconductor substrate is smaller than 2.5×10 17 cm −3 .

11 . The vertical power semiconductor device of claim 1 , wherein an oxygen concentration in at least part of the semiconductor substrate increases along the vertical direction toward the second main surface.

12 . The vertical power semiconductor device of claim 1 , wherein an oxygen concentration in at least part of the semiconductor substrate decreases along a lateral direction perpendicular to the vertical direction.

13 . The vertical power semiconductor device of claim 1 , wherein an oxygen concentration in at least part of the semiconductor substrate includes a plurality of minima and maxima alternately disposed along a lateral direction perpendicular to the vertical direction.

14 . A method for manufacturing a vertical power semiconductor device, the method comprising:
providing a semiconductor body by forming a semiconductor layer on a semiconductor substrate, wherein the semiconductor body has a first main surface and a second main surface opposite to the first main surface along a vertical direction; forming a drift region in the semiconductor body, wherein a first part of the drift region is arranged in the semiconductor substrate and a second part of the drift region is arranged in the semiconductor layer; and forming a field stop region arranged in the semiconductor substrate, wherein a doping concentration of the field stop region averaged along the vertical direction is larger than a doping concentration of the drift region averaged along the vertical direction.

15 . The method of claim 14 , wherein a vertical extension of the first part ranges from 10% to 90% of a vertical extension of the drift region.

16 . The method of claim 14 , wherein at least part of the semiconductor layer is formed on the semiconductor substrate by at least one epitaxial layer deposition process up to a vertical extension ranging from 50 μm to 300 μm.

17 . The method of claim 14 , wherein at least part of the semiconductor layer is formed on the semiconductor substrate by a bonding process using a donor substrate.

18 . The method of claim 14 , further comprising:
before forming the field stop region, reducing a vertical extension of the semiconductor substrate by removing material of the semiconductor substrate.

19 . The method of claim 14 , further comprising:
before forming the semiconductor layer on the semiconductor substrate, diffusing oxygen out of the semiconductor substrate by thermal processing.

20 . The method of claim 19 , further comprising:
before forming the semiconductor layer on the semiconductor substrate, forming a plurality of trenches into the semiconductor substrate.

21 . The method of claim 20 , wherein a lateral distance between neighboring two of the plurality of trenches is set in a range from 5 μm to 50 μm.

22 . The method of claim 14 , wherein the semiconductor substrate is a Czochralski (CZ) semiconductor substrate.

23 . The method of claim 22 , wherein the CZ semiconductor substrate is a Magnetic Czochralski (MCZ) semiconductor substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Schulze Hans-Joachim
• Kohler-Redlich Philipp
• Laska Thomas
• Niedernostheide Franz-Josef
• Van Treek Vera

Classifications

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H10D62/40

  Crystalline structures · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title