Power semiconductor device

Patent metadata

Field	Value
Publication number	US-2022013432-A1
Application number	US-201917293168-A
Country	US
Kind code	A1
Filing date	Nov 5, 2019
Priority date	Nov 21, 2018
Publication date	Jan 13, 2022
Grant date	—

Abstract

A power semiconductor device includes an insulating substrate on which a first conductor layer is arranged on one surface, a first conductor that is connected to the first conductor layer via a first connecting material, and a semiconductor element that is connected to the first conductor via a first connecting material. When viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first conductor includes a peripheral portion formed larger than the semiconductor element. A first recess is formed in the peripheral portion so that a thickness of the first connecting material becomes thicker than other portions.

First claim

1 . A power semiconductor device, comprising:
a first insulating substrate on which a first conductor layer is arranged on one surface; a first conductor that is connected to the first conductor layer via a first connecting material; and a semiconductor element that is connected to the first conductor via a second connecting material, wherein, when viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first conductor includes a peripheral portion formed larger than the semiconductor element, and a first recess is formed in the peripheral portion so that a thickness of the first connecting material becomes thicker than other portions.

2 . The power semiconductor device according to claim 1 , comprising:
a second conductor in which the semiconductor element is connected to a surface opposite to a surface to which the first conductor is connected via a fourth connecting material; and a second insulating substrate on which a third conductor layer is arranged on one surface, wherein, when viewed from a direction perpendicular to an electrode surface of the semiconductor element, the second conductor includes a peripheral portion formed larger than the semiconductor element, and a second recess is formed in the peripheral portion so that a thickness of the fifth connecting material becomes thicker than other portions.

3 . The power semiconductor device according to claim 1 , wherein, when viewed from a direction perpendicular to an electrode surface of the semiconductor element, a depth of the first recess is larger on a side farther from the semiconductor element than on a side closer to the semiconductor element.

4 . The power semiconductor device according to claim 1 , wherein, when viewed from a direction perpendicular to an electrode surface of the semiconductor element, if a length in a width direction parallel to the electrode surface is defined as W and a length in a depth direction is defined as D in the first recess, W/D is 2 or more.

5 . The power semiconductor device according to claim 1 , wherein
the first conductor includes a protrusion that forms a side portion of the recess on a side close to an outer circumference of the first connecting material, and the protrusion comes into contact with the first connecting material.

6 . The power semiconductor device according to claim 5 , wherein the protrusion comes into contact with the first conductor layer.

7 . The power semiconductor device according to claim 1 , wherein, when viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first recess is formed between a virtual line composed of a set of points separated from an end of the semiconductor element by a thickness of the first conductor and an outer circumference of the first conductor.

8 . The power semiconductor device according to claim 1 , wherein
the insulating substrate has a second conductor layer arranged on another surface, and a heat dissipation portion is provided to be connected to the second conductor layer via a third connecting material.

9 . The power semiconductor device according to claim 1 , wherein
when viewed from an arrangement direction of the first conductor layer and the second conductor layer, the heat dissipation portion has a second peripheral portion formed larger than the first conductor, and a third recess is formed in the second peripheral portion to make a thickness of the third connecting material thicker than other portions.

10 . The power semiconductor device according to claim 1 , wherein
the insulating substrate has a second conductor layer arranged on another surface, and the second conductor layer has fins for heat dissipation.

11 . The power semiconductor device according to claim 1 , wherein
the peripheral portion is composed of a first side on which the first recess is formed and a second side on which no recess is formed, and the semiconductor element is arranged so that a distance from the semiconductor element to the first side is smaller than a distance from the semiconductor element to the second side.

12 . The power semiconductor device according to claim 1 , comprising
a sealing member for sealing the insulating substrate, the first conductor, and the semiconductor element, wherein a depth of the first recess is smaller than a length of a side surface of the first conductor along the depth direction.

13 . The power semiconductor device according to claim 1 , wherein two or more semiconductor elements are provided on the first conductor.

14 . A method of manufacturing a power semiconductor device, comprising:
a first step of forming a first recess in a first conductor along a pulling-out direction by pulling-out; a second step of arranging a first conductor layer of an insulating substrate in a surface of the first conductor, where the first recess is formed, via a first connecting material, and arranging a semiconductor element in a surface on an opposite side of the surface, where the first recess is formed, via another connecting material; and a third step of melting the first connecting material such that a thickness of the first connecting material in the first recess becomes thicker than the first connecting material in other portions.

15 . The method of manufacturing the power semiconductor device according to claim 14 , wherein, in the second step, the semiconductor element is arranged such that a distance from the semiconductor element to the first recess is smaller than a distance from the semiconductor element to one side on which the recess of the first conductor is not formed.

Assignees

• Hitachi Astemo Ltd

Inventors

• Shimazu Hiromi
• Kaneko Yujiro
• Kato Toru
• Matsushita Akira
• Ide Eiichi

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W40/47

  by flowing liquids, e.g. forced water cooling · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W40/226

  characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461) · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title