Shielded fan-out packaged semiconductor device and method of manufacturing

Patent metadata

Field	Value
Publication number	US-2022013421-A1
Application number	US-202117483175-A
Country	US
Kind code	A1
Filing date	Sep 23, 2021
Priority date	Jul 28, 2017
Publication date	Jan 13, 2022
Grant date	—

Abstract

Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant.

First claim

I/We claim:

1 . A packaged semiconductor device, comprising:
a redistribution structure having first side, a second side, a dielectric formation having a thickness from the first side to the second side, die contacts at the first side of the redistribution structure, at least one shield contact at the first side of the redistribution structure, and ball external pads at the second side of the redistribution structure; a foundation deposited on the first side of the redistribution structure, wherein the foundation has openings and is spaced laterally apart from the outer perimeter of the semiconductor die, wherein the opening is configured to receive deposited conductive material; a semiconductor die mounted on the first side of the redistribution structure, wherein the semiconductor die has an outer perimeter and is laterally offset from the foundation; a conductive wall on the first side of the redistribution structure spaced laterally apart from the outer perimeter of the semiconductor die, wherein the conductive wall is in the openings of the foundation, electrically coupled to the shield contact, and extends around at least a portion of the outer perimeter of the semiconductor die; an encapsulant covering at least a portion of the semiconductor die and extending laterally outward with respect to the outer perimeter of the semiconductor die; and a conductive cap attached to the encapsulant and electrically coupled to the conductive wall such that the conductive wall and the conductive cap form a shield configured to protect the semiconductor die from electromagnetic interference.

2 . The packaged semiconductor device of claim 1 , wherein the foundation surrounds and directly contacts at least a pair of opposing boundaries of the conductive wall.

3 . The packaged semiconductor device of claim 1 , wherein the foundation is configured to define a pair of opposing peripheral edges of the conductive wall.

4 . The packaged semiconductor device of claim 3 , wherein the foundation is configured to receive and contain, along lateral directions, conductive past corresponding to formation of the conductive wall.

5 . The packaged semiconductor device of claim 3 , wherein the foundation is configured to receive and contain, along lateral directions, three-dimensionally printed conductive material corresponding to formation of the conductive wall.

6 . The packaged semiconductor device of claim 3 , wherein the foundation is configured to receive and contain, along lateral directions, metallization deposits corresponding to formation of the conductive wall.

7 . The packaged semiconductor device of claim 1 , wherein the conductive wall includes a top surface coplanar with a top surface of the encapsulant.

8 . The packaged semiconductor device of claim 7 , wherein the coplanar top surfaces of the conductive wall and the encapsulant include surface features corresponding to a singular removal process that simultaneously forms the coplanar top surfaces.

9 . The packaged semiconductor device of claim 1 , further comprising:
a second semiconductor die attached to the first side of the redistribution structure at a location spaced laterally apart from the semiconductor die; and a conductive inner partition formed on the first side of the redistribution structure and electrically coupled to the shield contact, wherein the conductive inner partition is between the semiconductor dies.

10 . The packaged semiconductor device of claim 1 , wherein the conductive wall directly contacts the first side of the redistribution structure and the encapsulant.

11 . A packaged semiconductor device, comprising:
a redistribution structure having first side, a second side, a dielectric formation having a thickness from the first side to the second side, die contacts at the first side of the redistribution structure, at least one shield contact at the first side of the redistribution structure, and external pads at the second side of the redistribution structure; a semiconductor die mounted on the first side of the redistribution structure, wherein the semiconductor die has an outer perimeter; an encapsulant covering at least a portion of the semiconductor die and extending laterally outward with respect to the outer perimeter of the semiconductor die; a conductive wall on the first side of the redistribution structure spaced laterally apart from the outer perimeter of the semiconductor die, wherein the conductive wall is electrically coupled to the shield contact and extends around at least a portion of the outer perimeter of the semiconductor die, the conductive wall having (1) a conductive top surface coplanar with a top surface of the encapsulant and (2) opposing vertical surfaces that (a) extend from the first side of the redistribution structure to the conductive top surface and toward each other and (b) directly contact the encapsulant; and a conductive cap attached to the encapsulant and electrically coupled to the conductive wall such that the conductive wall and the conductive cap form a shield configured to protect the semiconductor die from electromagnetic interference.

12 . The packaged semiconductor device of claim 11 , wherein the conductive wall has a trapezoidal cross-sectional shape.

13 . The packaged semiconductor device of claim 11 , wherein the conductive wall has vertical peripheral edges that are curved.

14 . The packaged semiconductor device of claim 13 , wherein the vertical peripheral edges of the conductive wall have convex shapes.

15 . The packaged semiconductor device of claim 13 , wherein opposing pairs of the vertical peripheral edges protrude away from each other.

16 . The packaged semiconductor device of claim 11 , further comprising a foundation on the first side of the redistribution structure, the foundation defining one or more openings, wherein the conductive wall is located within the one or more openings.

17 . The packaged semiconductor device of claim 16 , wherein the foundation directly contacts peripheral portions of the conductive wall and is configured to contain conductive material along lateral directions during manufacturing of the conductive wall that includes the contained conductive material.

18 . The packaged semiconductor device of claim 16 , wherein the foundation is configured to surround and contain the conductive material deposited via a three-dimensional printing process or a metallization deposit process.

19 . The packaged semiconductor device of claim 18 , wherein the conductive wall has a peripheral edge shape characteristic of a process used to deposit the conductive material.

20 . The packaged semiconductor device of claim 11 , wherein the coplanar top surfaces of the conductive wall and the encapsulant include surface features corresponding to a singular removal process that simultaneously forms the coplanar top surfaces.

Assignees

• Micron Technology Inc

Inventors

• Watanabe Fumitomo
• Kusanagi Keiyo

Classifications

• H10W42/273

  the arrangements being between laterally adjacent chips, e.g. walls between chips · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title