Resistive memory device

Patent metadata

Field	Value
Publication number	US-2022013171-A1
Application number	US-202117361534-A
Country	US
Kind code	A1
Filing date	Jun 29, 2021
Priority date	Jul 8, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.

First claim

What is claimed is:

1 . A resistive memory device comprising:
a first word line extending in a first horizontal direction in a cell array area and a cell wire area surrounding the cell array area on a substrate; a second word line arranged on the first word line in a vertical direction and extending in the first horizontal direction in the cell array area and the cell wire area; a third word line arranged on the second word line in the vertical direction and extending in the first horizontal direction in the cell array area and the cell wire area; a first bit line extending between the first and second word lines in a second horizontal direction perpendicular to the first horizontal direction in the cell array area and the cell wire area; a second bit line extending between the second word line and the third word line in the second horizontal direction in the cell array area and the cell wire area; and a plurality of memory cells respectively arranged at intersection points between the word lines and the bit lines in the cell array area, wherein a thickness of the second word line is greater than a thickness of each of the first word line and the third word line in the vertical direction.

2 . The resistive memory device of claim 1 , further comprising:
a first word line driver arranged in a first circuit area on the substrate; and a second word line driver arranged in a second circuit area separated from the first circuit area on the substrate in the first horizontal direction, wherein the first word line and the third word line are respectively connected to the first word line driver through a first wire structure, and wherein the second word line is connected to the second word line driver through a second wire structure.

3 . The resistive memory device of claim 1 , further comprising a peripheral circuit structure overlapping the cell array area and the cell wire area in the vertical direction, wherein the peripheral circuit structure comprises:
a first circuit area comprising a first word line driver; a second circuit area separated from the first circuit area in the first horizontal direction and comprising a second word line driver; and a plurality of wire layers arranged in the first circuit area and the second circuit area, wherein the first word line and the third word line are respectively connected to the first word line driver through a first wire structure comprising a first wire layer selected from among the plurality of wire layers, and wherein the second word line is connected to the second word line driver through a second wire structure comprising a second wire layer selected from among the plurality of wire layers, and the second wire structure is separated from the first wire structure.

4 . The resistive memory device of claim 3 , wherein the first wire structure comprises:
a first contact plug connected between the first wire layer and the second word line in the first circuit area; and a contact structure comprising a plurality of contact plugs connected in series between the first wire layer and the third word line in the vertical direction in the cell wire area, and wherein the contact structure is separated from the first contact plug in the second horizontal direction.

5 . The resistive memory device of claim 3 , wherein the first wire structure comprises:
a first contact plug connected between the first wire layer and the first word line in the first circuit area; and a contact structure comprising a plurality of contact plugs connected in series between the first word line and the third word line in the vertical direction in the cell wire area.

6 . The resistive memory device of claim 1 , further comprising:
a first word line driver arranged in a first circuit area between the substrate and the cell array area and electrically connected to the first word line and the third word line; a second word line driver arranged in a second circuit area separated from the first circuit area in the first horizontal direction and between the substrate and the cell array area, and configured to be electrically connected to the second word line; a first bit line driver arranged in a third circuit area between the substrate and the cell wire area and configured to be electrically connected to the first bit line; and a second bit line driver arranged in a fourth circuit area separated from the third circuit area in the second horizontal direction and between the substrate and the cell wire area, and configured to be electrically connected to the second bit line.

7 . The resistive memory device of claim 1 , wherein the first word line, the second word line, and the third word line comprise a same material.

8 . The resistive memory device of claim 1 , wherein the first word line and the third word line each comprise a first metal layer having a first resistivity, and
the second word line comprises a second metal layer having a second resistivity that is lower than the first resistivity.

9 . The resistive memory device of claim 1 , wherein the first word line comprises:
a first local portion linearly extending in the cell wire area in the first horizontal direction; and a second local portion linearly extending in the second horizontal direction, and a curved portion in which the first local portion meets the second local portion.

10 . The resistive memory device of claim 1 , wherein, in the cell wire area, the first word line has a first thickness in the vertical direction, and the third word line has a second thickness that is greater than the first thickness in the vertical direction.

11 . A resistive memory device comprising:
a plurality of first word lines arranged in parallel with each other in a cell array area and a cell wire area on a substrate, connected to a first word line driver arranged in a first circuit area on the substrate, and having a first thickness in a vertical direction; a plurality of second word lines arranged in parallel with each other in the first horizontal direction at locations separated from the plurality of first word lines in a vertical direction, connected to a second word line driver arranged in a second circuit area separated from the first circuit area in the first horizontal direction, and having a second thickness that is greater than the first thickness in the vertical direction; a plurality of third word lines arranged in parallel with each other in the first horizontal direction at locations separated from the plurality of first word lines in the vertical direction with the plurality of second word lines therebetween, connected to the first word line driver, and having a third thickness that is less than the second thickness in the vertical direction; a plurality of first bit lines arranged in parallel with each other in a second horizontal direction between the plurality of first word lines and the plurality of second word lines; a plurality of second bit lines arranged in parallel with each other in the second horizontal direction between the plurality of second word lines and the plurality of third word lines; and a plurality of memory cells arranged at points between the bit lines and the word lines in the cell array area.

12 . The resistive memory device of claim 11 , further comprising a peripheral circuit structure comprising the first circuit area and the second circuit area that are respectively arranged between the substrate and the plurality of first word lines in the vertical direction,
wherein a selected one of the plurality of first word lines and a selected one of the plurality of third word lines are respectively connected to the first word l

Assignees

• Samsung Electronics Co Ltd

Inventors

• Terai Masayuki

Classifications

• G11C2213/71

  Three dimensional array · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/0028 Primary

  Word-line or row circuits · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title