Memory controller, memory system including the same, and method of operating the memory controller

Patent metadata

Field	Value
Publication number	US-2022012128-A1
Application number	US-202117448995-A
Country	US
Kind code	A1
Filing date	Sep 27, 2021
Priority date	Apr 29, 2019
Publication date	Jan 13, 2022
Grant date	—

Abstract

A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device including a plurality of memory cells; and a memory controller including a processor, an error correction code (ECC) circuit, an error type detection circuit and a data patterning circuit, wherein the processor is configured to control overall operations of the memory controller, the ECC circuit is configured to perform an error detection and/or an error correction on first read data to generate first correction data and error bit information, the error type detection circuit is configured to receive the first correction data and the error bit information, to generate first write data based on the first correction data and the error bit information, to output the first write data to the memory device, to receive second read data that is obtained by reading the first write data written to the memory device, to perform an operation of comparing the second read data with the first write data, and to identify error type information based on the operation of comparing, and the data patterning circuit is configured to receive third data from an external host, to receive the error type information from the error type detection circuit, to randomize the third data based on the error type information to generate second write data, and to write the second write data to the memory device.

2 . The memory system of claim 1 , wherein the error type detection circuit detects an error bit of the second read data.

3 . The memory system of claim 1 , wherein the data patterning logic changes a bit pattern of the third data.

4 . The memory system of claim 1 , wherein the memory controller includes a random access memory (RAM), a host interface and a memory interface.

5 . The memory system of claim 1 , wherein the memory controller performs an operation of rewriting the same data to the plurality of memory cells of the memory device.

6 . The memory system of claim 1 , wherein the first read data includes data bits and parity bits.

7 . The memory system of claim 1 , wherein in case that the ECC circuit fails the error correction on the first read data, the ECC circuit performs a read retry operation by entering a defensive code.

8 . The memory system of claim 1 , wherein in case that the error correction on the first read data is successful, the ECC circuit writes the first write data to the memory device when the number of error bits exceeds a threshold value.

9 . The memory system of claim 1 , wherein in case that the error correction on the first read data is successful, the ECC circuit does not write the first write data to the memory device and keeps the first read data in the memory device when the number of error bits is less than or equal to a threshold value.

10 . The memory system of claim 1 , wherein the memory device is a phase change random access memory (PRAM).

11 . A memory controller comprising:
a processor configured to control overall operations of the memory controller, an error correction code (ECC) circuit configured to perform an error detection and/or an error correction on first read data to generate first correction data and error bit information; an error type detection circuit configured to receive the first correction data and the error bit information, to generate first write data based on the first correction data and the error bit information, to output the first write data to an external memory device, to receive second read data that is obtained by reading the first write data written to the external memory device, to perform an operation of comparing the second read data with the first write data, and to identify error type information based on the operation of comparing; and a data patterning circuit configured to receive third data from an external host, to receive the error type information from the error type detection circuit, to randomize the third data based on the error type information to generate second write data, and to write the second write data to the external memory device.

12 . The memory controller of claim 11 , wherein an error type on the second read data includes a temporary error and a stuck error.

13 . The memory controller of claim 11 , wherein the first read data includes data bits and parity bits.

14 . The memory controller of claim 11 , wherein the memory controller performs an operation of rewriting the same data to a plurality of memory cells of the external memory device.

15 . A method comprising:
reading, by a memory controller, first read data stored in a memory device; performing, by the memory controller, an error detection and/or an error correction on the first read data to generate first correction data and error bit information; generating, by the memory controller, first write data based on the first correction data and the error bit information; storing, by the memory controller, the first write data in the memory device; obtaining, by the memory controller, second read data by reading the first write data stored in the memory device; comparing, by the memory controller, the second read data with the first write data to generate error type information; receiving, by the memory controller, third data from a host; randomizing, by the memory controller, the third data based on the error type information to generate second write data; and writing the second write data to the memory device.

16 . The method of claim 15 , further comprising performing a read retry operation by entering a defensive code when the error correction on the first read data fails.

17 . The method of claim 15 , wherein an error type on the second read data includes a temporary error and a stuck error.

18 . The method of claim 15 , further comprising detecting an error bit of the second read data.

19 . The method of claim 15 , wherein the first read data includes data bits and parity bits.

20 . The method of claim 15 , wherein the memory device is a phase change random access memory (PRAM).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeongho
• Kim Youngsik
• Baek Seungyou
• Oh Eunchu
• Yoo Youngkwang
• Lee Younggeun

Classifications

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title