Resource management controller

US2022012094A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022012094-A1
Application numberUS-202117481940-A
CountryUS
Kind codeA1
Filing dateSep 22, 2021
Priority dateSep 22, 2021
Publication dateJan 13, 2022
Grant date

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. Other embodiments are disclosed and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic apparatus, comprising: one or more substrates; and a controller coupled to the one or more substrates, the controller including circuitry to: read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. 2 . The apparatus of claim 1 , wherein the utilization-related information includes run-time telemetry for the resource. 3 . The apparatus of claim 1 , wherein the circuitry is further to: schedule utilization of the resource based on a priority associated with the request and the utilization-related information for the resource. 4 . The apparatus of claim 1 , wherein the circuitry is further to: handle a page-fault in response to the request from the processor. 5 . The apparatus of claim 1 , wherein the circuitry is further to: determine if the utilization of the resource responsive to the request from the processor is complete; and, if so determined, notify the processor that the request is completed. 6 . The apparatus of claim 1 , wherein the circuitry is further to: interface with an agent to schedule resource utilization of a remote resource. 7 . The apparatus of claim 1 , wherein the circuitry is further to: read run-time bandwidth information from the shared memory for two or more resources in response to the request from the processor; and perform an on-the-fly selection among the two or more resources based on the run-time bandwidth information. 8 . The apparatus of claim 1 , wherein the circuitry is further to: read run-time internal resource utilization information from the shared memory for a non-volatile memory in response to the request from the processor; and schedule utilization of the non-volatile memory based on a priority associated with the request and the run-time internal resource utilization information for the non-volatile memory. 9 . An electronic system, comprising: a processor; memory communicatively coupled to the processor; and a controller communicatively coupled to the processor and the memory, the controller including circuitry to: read utilization-related information for a resource from the memory in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. 10 . The system of claim 9 , wherein the utilization-related information includes run-time telemetry for the resource. 11 . The system of claim 9 , wherein the circuitry is further to: schedule utilization of the resource based on a priority associated with the request and the utilization-related information for the resource. 12 . The system of claim 9 , wherein the circuitry is further to: handle a page-fault in response to the request from the processor. 13 . The system of claim 9 , wherein the circuitry is further to: interface with an agent to schedule resource utilization of a remote resource. 14 . The system of claim 9 , wherein the circuitry is further to: read run-time internal resource utilization information from the memory for a non-volatile memory in response to the request from the processor; and schedule utilization of the non-volatile memory based on a priority associated with the request and the run-time internal resource utilization information for the non-volatile memory. 15 . A method of managing a resource, comprising: reading utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource; and scheduling utilization of the resource based at least in part on the utilization-related information for the resource. 16 . The method of claim 15 , wherein the utilization-related information includes run-time telemetry for the resource. 17 . The method of claim 15 , further comprising: scheduling utilization of the resource based on a priority associated with the request and the utilization-related information for the resource. 18 . The method of claim 15 , further comprising: handling a page-fault in response to the request from the processor. 19 . The method of claim 15 , further comprising: interfacing with an agent to schedule resource utilization of a remote resource. 20 . The method of claim 15 , further comprising: reading run-time bandwidth information from the shared memory for two or more resources in response to the request from the processor; and performing an on-the-fly selection among the two or more resources based on the run-time bandwidth information.

Assignees

Inventors

Classifications

  • G06F9/5016Primary

    the resource being the memory · CPC title

  • G06F9/5005Primary

    to service a request · CPC title

  • Buffers; Shared memory; Pipes · CPC title

  • using a common memory, e.g. mailbox · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2022012094A1 cover?
An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the ut…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F9/5016. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jan 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).