Analog multiply-accumulate unit for multibit in-memory cell computing

Patent metadata

Field	Value
Publication number	US-2022012016-A1
Application number	US-202117485179-A
Country	US
Kind code	A1
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Jan 13, 2022
Grant date	—

Abstract

Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

First claim

We claim:

1 . A computing system comprising:
a processor; a memory array; and a multiply-accumulator (MAC), wherein the MAC includes a first plurality of multipliers that includes a plurality of capacitors, wherein the first plurality of multipliers is configured to:
receive first digital signals from the memory array,
execute multibit computation operations with the plurality of capacitors based on the first digital signals, and
generate a first analog signal based on the multibit computation operations.

2 . The computing system of claim 1 , wherein:
the plurality of capacitors includes a first group of capacitors and a second group of capacitors, the first plurality of multipliers further comprises:
a plurality of switches, and
a plurality of branches that include the plurality of switches and the first group of capacitors.

3 . The computing system of claim 2 , wherein the second group of capacitors connect the plurality of branches, further wherein a capacitance of the second group of capacitors is greater than a capacitance of the first group of capacitors.

4 . The computing system of claim 2 , wherein the plurality of switches is to be configured to electrically connect or disconnect from an input analog signal based on the first digital signals.

5 . The computing system of claim 4 , wherein the plurality of capacitors and the plurality of switches form a C-2C ladder.

6 . The computing system of claim 1 , wherein the plurality of capacitors includes a plurality of pairs of capacitors that each correspond to a different bit.

7 . The computing system of claim 1 , wherein the MAC further comprises:
a second plurality of multipliers that includes a second plurality of capacitors that is to generate a second analog signal based on second digital signals; and an adder to add the first and second analog signal.

8 . The computing system of claim 1 , wherein the first digital signals are associated with weights of a neural network.

9 . A semiconductor apparatus comprising:
one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic and comprising:
a memory array; and
a multiply-accumulator (MAC) connected to the memory array, wherein the MAC includes a first plurality of multipliers that includes a plurality of capacitors, wherein the first plurality of multipliers is configured to:
receive first digital signals from the memory array;
execute multibit computation operations with the plurality of capacitors based on the first digital signals; and
generate a first analog signal based on the multibit computation operations.

10 . The apparatus of claim 9 , wherein:
the plurality of capacitors includes a first group of capacitors and a second group of capacitors, the first plurality of multipliers further comprises:
a plurality of switches; and
a plurality of branches that include the plurality of switches and the first group of capacitors.

11 . The apparatus of claim 10 , wherein the second group of capacitors connect the plurality of branches, further wherein a capacitance of the second group of capacitors is greater than a capacitance of the first group of capacitors.

12 . The apparatus of claim 10 , wherein the plurality of switches is to be configured to electrically connect or disconnect from an input analog signal based on the first digital signals.

13 . The apparatus of claim 9 , wherein the plurality of capacitors and the plurality of switches form a C-2C ladder.

14 . The apparatus of claim 9 , wherein the plurality of capacitors includes a plurality of pairs of capacitors that each correspond to a different bit.

15 . The apparatus of claim 9 , wherein the MAC further comprises:
a second plurality of multipliers that includes a second plurality of capacitors that is to generate a second analog signal based on second digital signals; and an adder to add the first and second analog signal.

16 . The apparatus of claim 9 , wherein the first digital signals are associated with weights of a neural network.

17 . The apparatus of claim 9 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

18 . A method comprising:
receiving, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors; executing, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals; and generating, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

19 . The method of claim 18 , wherein:
the plurality of capacitors includes a first group of capacitors and a second group of capacitors, the first plurality of multipliers further comprises:
a plurality of switches; and
a plurality of branches that include the plurality of switches and the first group of capacitors.

20 . The method of claim 19 , wherein the second group of capacitors connect the plurality of branches, further wherein a capacitance of the second group of capacitors is greater than a capacitance of the first group of capacitors.

21 . The method of claim 19 , wherein the plurality of switches is configured to electrically connect or disconnect from an input analog signal based on the first digital signals.

22 . The method of claim 18 , wherein the plurality of capacitors and the plurality of switches form a C-2C ladder.

23 . The method of claim 18 , wherein the plurality of capacitors includes a plurality of pairs of capacitors that each correspond to a different bit.

24 . The method of claim 18 , further comprising:
generating, with a second plurality of multipliers of the MAC, a second analog signal based on second digital signals, wherein the second plurality of multipliers includes a second plurality of capacitors; and adding the first and second analog signal.

25 . The method of claim 18 , wherein the first digital signals are associated with weights of a neural network.

Assignees

• Intel Corp

Inventors

• Wang Hechen
• Liu Renzhi
• Dorrance Richard
• Dasalukunte Deepak

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• H03M1/80

  using weighted impedances (H03M1/76 takes precedence) · CPC title

• H03M1/78

  using ladder network · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title