Memory controller, storage device and memory system

Patent metadata

Field	Value
Publication number	US-2022011978-A1
Application number	US-202117321919-A
Country	US
Kind code	A1
Filing date	May 17, 2021
Priority date	Jul 9, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A memory controller configured to control a non-volatile memory device includes: a signal generator configured to generate a plurality of control signals comprising a first signal and a second control signal; a core configured to provide a command for an operation of the non-volatile device; and a controller interface circuit configured to interface with the non-volatile memory device, wherein the controller interface circuit comprises a first transmitter connected to a first signal line and a second signal line; and a first receiver connected to the first signal line, and the first control signal and the second control signal are respectively transmitted to the non-volatile memory device through the first signal line and the second signal line.

First claim

What is claimed is:

1 . A memory controller configured to control a non-volatile memory device, the memory controller comprising:
a signal generator configured to generate a plurality of control signals comprising a first control signal and a second control signal; a core configured to provide a command for an operation of the memory device; and a controller interface circuit configured to interface with the memory device, wherein the controller interface circuit comprises a first transmitter connected to a first signal line and a second signal line, and a first receiver connected to the first signal line, and wherein the first control signal and the second control signal are respectively transmitted to the memory device through the first signal line and the second signal line.

2 . The memory controller of claim 1 , wherein:
the first control signal is a data strobe signal, the second control signal is an inverse data strobe signal, the data strobe signal synchronizes input of the data and output of the data, and the inverse data strobe signal is a phase inversion signal of the data strobe signal.

3 . The memory controller of claim 1 , wherein:
the first transmitter is configured to apply a single fully differential interconnection method, and the first receiver is configured to apply a single-ended interconnection method.

4 . The memory controller of claim 1 , wherein”
the plurality of control signals further comprise a third control signal and a fourth control signal, and
the controller interface circuit further comprises a second transmitter configured to transmit the third control signal and the fourth control signal.

5 . The memory controller of claim 4 , wherein:
the third control signal is a read enable signal, the fourth control signal is an inverse read enable signal, the read enable signal is toggled to continuously read data from the non-volatile memory device, and the inverse read enable signal is a phase inversion signal of the read enable signal.

6 . The memory controller of claim 1 , wherein the controller interface circuit further comprises:
a first pin through which a data strobe signal synchronizing input data and output data is transmitted; a second pin through which the data strobe signal is inverted and transmitted; a third pin through which a read enable signal toggled for reading data is transmitted; a fourth pin through which the read enable signal is inverted and transmitted; and a fifth pin through which the command, address, and data are transmitted.

7 . The memory controller of claim 1 , wherein the controller interface circuit further comprises a multiplexer connected to the first receiver.

8 . The memory controller of claim 7 , wherein:
the first receiver receives a fifth control signal for data synchronization after the first control signal is transmitted through the first signal line, and the multiplexer multiplexes a sixth control signal for data synchronization with a reference voltage signal after the second control signal is transmitted through the second signal line.

9 . A storage device comprising:
a non-volatile memory device; and a memory controller configured to control the non-volatile memory device by providing to the non-volatile memory device a command, an address, data, and a control signal, wherein the memory controller comprises a controller interface comprising a first transmitter configured to apply a differential interconnection method, a first receiver configured to apply a single-ended interconnection method, and a controller interface circuit configured to interface with the non-volatile memory device, and wherein the non-volatile memory device comprises a memory interface circuit comprising a second transmitter and a second receiver, the memory interface circuit configured to interface with the memory controller.

10 . The storage device of claim 9 , wherein the controller interface circuit further comprises:
a first pin through which a data strobe signal synchronizing data input/output is transmitted; a second pin through which the data strobe signal is inverted and transmitted; a third pin through which a read enable signal toggled for reading data is transmitted; a fourth pin through which the read enable signal is inverted and transmitted; and a fifth pin through which the command, address, and data are transmitted.

11 . The storage device of claim 10 , wherein the memory interface circuit further comprises:
a sixth pin corresponding to the first pin; a seventh pin corresponding to the second pin; an eighth pin corresponding to the third pin; a ninth pin corresponding to the fourth pin; and a tenth pin corresponding to the fifth pin.

12 . The storage device of claim 11 , wherein:
the first receiver and the first transmitter receive and transmit the data strobe signal through the first pin, and the second receiver and the second transmitter receive and transmit the data strobe signal through the sixth pin.

13 . The storage device of claim 9 , wherein:
the controller interface circuit further comprises a multiplexer connected to the first receiver, the first receiver receives a data strobe signal from the memory interface circuit, the multiplexer multiplexes an inverse data strobe signal, which is received from the memory interface circuit, with a reference voltage signal, the data strobe signal synchronizes data input and data output, and the inverse data strobe signal is a phase inversion signal of the data strobe signal.

14 . The storage device of claim 9 , wherein:
the controller interface circuit further comprises a third transmitter configured to apply a fully differential interconnection method, and the memory interface circuit further comprises a third receiver that is configured to apply the single-ended differential interconnection method.

15 . The storage device of claim 9 , wherein the second transmitter and the second receiver are configured to apply the single-ended differential interconnection method.

16 . The storage device of claim 9 , wherein the second transmitter and the second receiver are configured to apply the fully differential interconnection method.

17 . A memory system comprising:
a first interface circuit comprising a first transmitter connected to a first signal line and a second signal line and a first receiver connected to the first signal line; and a second interface circuit comprising a second receiver connected to at least one of the first signal line and the second signal line and a second transmitter connected to at least one of the first signal line and the second signal line, wherein a first control signal and a second control signal are respectively transmitted to the second interface circuit through the first signal line and the second signal line, and the first receiver receives a third control signal for data synchronization after the first control signal is transmitted through the first signal line.

18 . The memory system of claim 17 , wherein:
the first interface circuit further comprises a multiplexer connected to the first receiver and configured to multiplex a fourth control signal for data synchronization with a reference voltage signal after the second control signal is transmitted through the second signal line, the first control signal and the third control signal are data strobe signals synchronizing data input and data output, and the second control signal and the fourth control signal are inverse data strobe signals obtained by

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Choongeui
• Lee Chulseung

Classifications

• G11C7/1093

  Input synchronization · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/24

  Bit-line control circuits · CPC title