Array Substrate and Method for Manufacturing the Same, and Display Device

Patent metadata

Field	Value
Publication number	US-2022005888-A1
Application number	US-201916759508-A
Country	US
Kind code	A1
Filing date	Jun 11, 2019
Priority date	Jun 11, 2019
Publication date	Jan 6, 2022
Grant date	—

Abstract

The present disclosure provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes: a base substrate; a photosensitive element located between the base substrate and a light emitting device and configured to sense light emitted from the light emitting device and generate a sensing signal according to the light; a capacitor configured to store the sensing signal; and a sensing transistor located between the base substrate and the photosensitive element and configured to transmit the sensing signal to a sensing line, wherein an orthographic projection of the sensing transistor on the base substrate at least partially overlaps with an orthographic projection of the photosensitive element on the base substrate.

First claim

1 . An array substrate, comprising:
a base substrate; a photosensitive element located between the base substrate and a light emitting device and configured to sense light emitted from the light emitting device and generate a sensing signal according to the light; a capacitor configured to store the sensing signal; and a sensing transistor located between the base substrate and the photosensitive element and configured to transmit the sensing signal to a sensing line, wherein an orthographic projection of the sensing transistor on the base substrate at least partially overlaps with an orthographic projection of the photosensitive element on the base substrate.

2 . The array substrate according to 1 , further comprising a first dielectric layer covering the sensing transistor, wherein:
the capacitor comprises: a first metal layer connected to the signal line and located on one side of the first dielectric layer away from the base substrate, a second dielectric layer located on the one side of the first dielectric layer away from the base substrate and one side of the first metal layer away from the base substrate, wherein an orthographic projection of the first metal layer on the base substrate is within an orthographic projection of the second dielectric layer on the base substrate, and a second metal layer located on one side of the second dielectric layer away from the base substrate and connected to a first electrode of the sensing transistor through a first via penetrating the second dielectric layer and the first dielectric layer; and the photosensitive element is located on one side of the second metal layer away from the base substrate.

3 . The array substrate according to 2 , wherein the second metal layer is partially located in the first via and in contact with the first electrode of the sensing transistor.

4 . The array substrate according to claim 2 , wherein the photosensitive element comprises a P-type semiconductor layer, and an N-type semiconductor layer located between the P-type semiconductor layer and the second metal layer.

5 . The array substrate according to claim 4 , further comprising:
a planarization layer located on the one side of the second dielectric layer away from the base substrate and one side of the P-type semiconductor layer away from the base substrate, wherein the planarization layer defines a first opening extending to the P-type semiconductor layer; and an electrode layer partially located in the first opening and in contact with the P-type semiconductor layer, wherein the electrode layer is connected to the metal layer through a second via penetrating the planarization layer and the second dielectric layer.

6 . The array substrate according to 5 , wherein the electrode layer is partially located in the second via and in contact with the first metal layer.

7 . The array substrate according to 2 , wherein the sensing transistor comprises:
an active layer; a gate dielectric layer located on one side of the active layer away from the base substrate; a gate located on one side of the gate dielectric layer away from the active layer; an interlayer dielectric layer located on one side of the gate dielectric layer away from the base substrate and covering the gate, wherein the interlayer dielectric layer defines a second opening and a third opening which extend to the active layer; and a second electrode at least partially located in the third opening and in contact with the active layer, and wherein the first electrode is at least partially located in the second opening and in contact with the active layer.

8 . The array substrate according to claim 4 , wherein the photosensitive element further comprises an intrinsic semiconductor layer located between the P-type semiconductor layer and the N-type semiconductor layer.

9 . The array substrate according to claim 8 , wherein a material of at least one of the P-type semiconductor layer, the N-type semiconductor layer, or the intrinsic semiconductor layer comprises hydrogen.

10 . The array substrate according to claim 1 , further comprising:
a driving transistor located between the base substrate and the light emitting device, wherein an orthographic projection of the driving transistor on the base substrate is spaced apart from the orthographic projection of the sensing transistor on the base substrate.

11 . The array substrate according to claim 1 , wherein the orthographic projection of the sensing transistor on the base substrate is within the orthographic projection of the photosensitive element on the base substrate.

12 . A display device, comprising the array substrate according to claim 1 .

13 . A method for manufacturing an array substrate, comprising:
providing a base substrate; forming a sensing transistor and a capacitor on one side of the base substrate; and forming a photosensitive element on one side of the sensing transistor away from the base substrate, wherein an orthographic projection of the photosensitive element on the base substrate at least partially overlaps with an orthographic projection of the sensing transistor on the base substrate, wherein: the photosensitive element is configured to sense light emitted from a light emitting device and generate a sensing signal according to the light, the capacitor is configured to store the sensing signal, and the sensing transistor is configured to transmit the sensing signal to a sensing line.

14 . The method according to claim 13 , further comprising forming a first dielectric layer covering the sensing transistor after forming the sensing transistor, wherein:
the forming of the capacitor comprises: forming a first metal layer connected to a signal line on one side of the first dielectric layer away from the base substrate, forming a second dielectric layer on the one side of the first dielectric layer away from the base substrate and one side of the first metal layer away from the base substrate, wherein an orthographic projection of the first metal layer on the base substrate is within an orthographic projection of the second dielectric layer on the base substrate, and forming a second metal layer on one side of the second dielectric layer away from the base substrate, wherein the second metal layer is connected to a first electrode of the sensing transistor through a first via penetrating the second dielectric layer and the first dielectric layer; and the forming of the photosensitive element comprises forming the photosensitive element on one side of the second metal layer away from the base substrate.

15 . The method according to claim 14 , wherein forming the photosensitive element comprises:
forming an N-type semiconductor layer on one side of the second metal layer away from the base substrate; and forming a P-type semiconductor layer on one side of the N-type semiconductor layer away from the base substrate.

16 . The method according to claim 15 , further comprising:
forming a planarization layer on the one side of the second dielectric layer away from the base substrate and one side of the P-type semiconductor layer away from the base substrate, wherein the planarization layer defines a first opening extending to the P-type semiconductor layer; and forming an electrode layer partially located in the first opening and in contact with the P-type semiconductor layer, wherein the electrode layer is connected to the first metal layer through a second via penetrating the planarization layer and the second dielectric layer.

17 . The method according to claim 14 , wh

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Guoying
• Song Zhen

Classifications

• H10K59/60 Primary

  OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title

• H10K59/13 Primary

  comprising photosensors that control luminance · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• H01L27/3244

  Electricity · mapped topic

• H01L2227/323

  Electricity · mapped topic