Integrated circuit including multiple height cell and method of designing the same

Patent metadata

Field	Value
Publication number	US-2022005801-A1
Application number	US-202117181672-A
Country	US
Kind code	A1
Filing date	Feb 22, 2021
Priority date	Jul 1, 2020
Publication date	Jan 6, 2022
Grant date	—

Abstract

An integrated circuit includes a standard cell continuously arranged on a first row and on a second row, the first row and second row extending parallel with each other in a first direction, the first row and the second row adjacent to each other in a second direction crossing the first direction, a first cell separator contacting a first row boundary of the standard cell on the first row and extending in the second direction, and a second cell separator contacting a second row boundary of the standard cell on the second row and extending in the second direction. The first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a standard cell continuously arranged on a first row and on a second row, the first row and second row extending parallel with each other in a first direction, the first row and the second row adjacent to each other in a second direction crossing the first direction; a first cell separator contacting a first row boundary of the standard cell on the first row and extending in the second direction; and a second cell separator contacting a second row boundary of the standard cell on the second row and extending in the second direction, wherein the first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row.

2 . The integrated circuit of claim 1 , wherein the standard cell comprises:
a first sub-cell on the first row; and a second sub-cell on the second row, wherein a first sub-cell boundary of the first sub-cell partially overlaps a second sub-cell boundary of the second sub-cell on the first row to second row boundary.

3 . The integrated circuit of claim 2 , wherein a length of the first sub-cell in the first direction is different from a length of the second sub-cell in the first direction.

4 . The integrated circuit of claim 2 , wherein the standard cell further comprises:
an internal connection pattern that (a) extends in the second direction, (b) electrically connects a conductive pattern of the first sub-cell to a conductive pattern of the second sub-cell, and (c) is arranged across the first row to second row boundary.

5 . The integrated circuit of claim 1 , wherein the standard cell further comprises:
a first active region group on the first row, the first active region group extending in the first direction; and a second active region group on the second row, the second active region group extending in the first direction, wherein the first cell separator terminates the first active region group, and the second cell separator terminates the second active region group.

6 . The integrated circuit of claim 1 , wherein a width of the first row is different from a width of the second row.

7 . The integrated circuit of claim 1 , wherein a cell boundary of the standard cell has a polygonal shape different from a rectangular shape.

8 . An integrated circuit comprising:
a first cell on a first row extending in a first direction; a second cell adjacent to the first row in a second direction crossing the first direction, the second cell on a second row and extending in the first direction; a third cell continuously arranged on the first row and the second row; a first cell separator between the first cell and the third cell, the first cell separator extending in the second direction; and a second cell separator between the second cell and the third cell, the second cell separator extending in the second direction, wherein the first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row.

9 . The integrated circuit of claim 8 , wherein the third cell comprises:
a first sub-cell on the first row; and a second sub-cell on the second row, wherein a boundary of the first sub-cell at least partially overlaps a second sub-cell boundary of the second sub-cell on the first row to second row boundary.

10 . The integrated circuit of claim 9 , wherein a first length of the first sub-cell in the first direction is different from a second length of the second sub-cell in the first direction.

11 . The integrated circuit of claim 9 , wherein the third cell further comprises:
an internal connection pattern extending in the second direction, and electrically connecting a first conductive pattern of the first sub-cell to a second conductive pattern of the second sub-cell.

12 . The integrated circuit of claim 9 , further comprising:
an external connection pattern connecting input/output fins included in the first through third cells.

13 . The integrated circuit of claim 8 , wherein the third cell further comprises:
a first active region group extending in the first direction on the first row; and a second active region group extending in the first direction on the second row, wherein the first cell separator terminates the first active region group, and the second cell separator terminates the second active region group.

14 . The integrated circuit of claim 8 , wherein a first width of the first row is different from a second width of the second row.

15 . The integrated circuit of claim 8 , wherein a third cell boundary of the third cell has a polygonal shape different from a rectangular shape.

16 . A method of designing an integrated circuit, the method comprising:
selecting a multiple height cell based on input data defining the integrated circuit, the multiple height cell comprising a first sub-cell and a second sub-cell; and arranging the multiple height cell on a first row and a second row extending parallel with each other in a first direction and adjacent to each other, wherein the arranging of the multiple height cell comprises,
arranging the first sub-cell on the first row,
arranging the second sub-cell on the second row, and
adding at least one internal connection pattern connecting a first conductive pattern of the first sub-cell to a second conductive pattern of the second sub-cell.

17 . The method of claim 16 , further comprising:
adding an external connection wiring connecting an input/output pin of the multiple height cell to an input/output pin of a cell adjacent to the multiple height cell.

18 . The method of claim 16 , wherein a first sub-cell boundary of the first sub-cell at least partially overlaps a second sub-cell boundary of the second sub-cell on a first row to second row boundary of the first row and the second row.

19 . The method of claim 18 , wherein a first length of the first sub-cell in the first direction is different from a second length of the second sub-cell in the first direction.

20 . The method of claim 16 , wherein a first width of the first row is different from a second width of the second row.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sungok
• Park Sangdo
• Cho Dayeon

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D89/00

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title