Systems and methods for analyzing stability using metal resistance variations

Patent metadata

Field	Value
Publication number	US-2021397415-A1
Application number	US-202117465462-A
Country	US
Kind code	A1
Filing date	Sep 2, 2021
Priority date	Aug 28, 2013
Publication date	Dec 23, 2021
Grant date	—

Abstract

This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

First claim

1 . A method for generating a digital value for a physically unclonable function comprising the steps of:
reviewing a chip bitstring from an integrated circuit; classifying each bit of the chip bitstring as a weak bit or a strong bit; constructing a bitstring using the classified bits; and creating redundant sequences within the constructed bitstring.

2 . The method of claim 1 , wherein the creating step further comprises the step of selecting a bit value for each redundant sequence by skipping bits within the chip bitstring.

3 . The method of claim 2 , wherein the bits skipped are:
the weak bits; or the strong bits that do not match a first bit of the redundant sequence within the constructed bitstring.

4 . The method of claim 2 , wherein a number (X) of bits in each redundant sequence is an odd number.

5 . The method of claim 4 , wherein the odd number is greater than or equal to 3.

6 . The method of claim 1 , wherein the classifying step further comprises the steps of:
computing a threshold range; and defining weak bits as those within the threshold range and defining strong bits as those either above the threshold range or below the threshold range.

7 . The method of claim 6 , wherein the threshold range is computed from a distribution of a plurality of power grid voltage differences.

8 . The method of claim 7 , wherein the threshold range is derived from a distance between a first point and a second point in the distribution with the first point located at a first percentage of the distribution and the second point located at a second percentage of the distribution.

9 . The method of claim 8 , wherein the first percentage is selected from the group of 5%, 10%, 15%, 20%.

10 . The method of claim 8 , wherein the second percentage is selected from the group of: 95%, 90%, 85%, 80%.

11 . The method of claim 1 , wherein the value of the first bit is ‘0’ or ‘1’.

12 . The method of claim 1 further comprising the step of recording in a public storage a position for each weak bit and each skipped strong bit in the sequence.

13 . The method of claim 1 further comprising the steps of:
comparing two or more redundant sequences;
selecting a final hit value as the value occurring the most often for a given bit position across the compared redundant sequences; and
constructing a final bitstring comprising a sequence of selected final bit values.

14 . A method for generating a digital value for a physically unclonable function comprising the steps of:
providing a bitstring comprising a sequence of bit values; using the sequence of bit values to create a set of bitstring sequences, the set comprising a number (X) of copied bitstrings, wherein X is odd and greater than or equal to 3; comparing the bitstring and the copied bitstrings; selecting a final bit value for each given bit position; and constructing a final bitstring comprising a sequence of selected final bit values.

15 . The method of claim 14 , wherein each selected final bit value is a value occurring the most often in a given bit position across the bitstring and the copied bitstrings.

16 . The method of claim 15 , wherein each bit value is a ‘1’ or a ‘0’;

17 . The method of claim 14 , wherein the final bitstring enables an integrated circuit to reproduce a sequence of strong bits.

18 . The method of claim 17 , wherein the integrated circuit reproduces the sequence of strong bits without bit flip errors.

19 . The method of claim 18 , wherein a number of bit flip errors is less than half a number of bits in the sequence of strong bits.

20 . The method of claim 14 , wherein the sequence of selected final bit values is of a length n and a number of strong bits (2*X−1)*n.

Assignees

• Unm Rainforest Innovations

Inventors

• Plusquellic James

Classifications

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• Y04S40/20

  Information technology specific aspects, e.g. CAD, simulation, modelling, system security · CPC title