Managing quality of service by allocating die parallelism with variable queue depth

US2021392083A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021392083-A1
Application numberUS-202117355915-A
CountryUS
Kind codeA1
Filing dateJun 23, 2021
Priority dateJun 23, 2021
Publication dateDec 16, 2021
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.

First claim

Opening claim text (preview).

We claim: 1 . A memory controller comprising: one or more substrates; and a logic coupled to the one or more substrates, where the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic to: determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis, wherein the projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters; and receive, from a host, a requested bandwidth level and a requested quality of service level in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels. 2 . The memory controller of claim 1 , wherein the one or more storage device parameters include one or more of a number of dies, an internal queue depth, a media operation speed, a per die read projection, a per die write projection, or a program or erase suspend projection. 3 . The memory controller of claim 2 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a command priority in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels; and control the internal queue depth to maintain the requested quality of service level, wherein the internal queue depth is controlled based at least in part on dynamically reallocating the command priority via the memory controller. 4 . The memory controller of claim 3 , wherein the logic coupled to the one or more substrates is to: receive, from a host, permission to dynamically reallocate the command priority via the memory controller. 5 . The memory controller of claim 3 , wherein the logic coupled to the one or more substrates is to: receive, from the host, instructions on how to dynamically reallocate the command priority. 6 . The memory controller of claim 3 , wherein the dynamic reallocation of the command priority for a first user includes configuring a first percentage of first user commands to be executed at a first priority and a second percentage of first user commands to be executed at a second priority, and wherein the first priority is different from the second priority. 7 . The memory controller of claim 3 , wherein the dynamic reallocation of the command priority is based at least in part on one or more of a change in the internal queue depth, a change in media type among a plurality of storage devices, a change in power management per user, or a change in defragment policy. 8 . The memory controller of claim 3 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a request for a current priority of a first user; and report the current priority of the first user to the host based on the dynamic reallocation of the command priority. 9 . The memory controller of claim 1 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a request for a change in media type among a plurality of storage devices; select a target storage device from the plurality of storage devices including a first storage device of a first media type and a second storage device of a second media type, wherein the second device is to operate more slowly than the first device; and issue an incoming user command to the target storage device. 10 . The memory controller of claim 9 , wherein the plurality of storage devices are to include one or more of a quad level cell solid state drive, a three-dimensional crosspoint solid state drive, or a three-dimensional crosspoint data center persistent memory. 11 . The memory controller of claim 1 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a requested garbage collection frequency for a garbage collection timer; and configure the garbage collection timer based on the requested garbage collection frequency. 12 . The memory controller of claim 1 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a request to activate a write aggregation and de-staging timer; and send, to the host, a report of completion when ready to accept de-staged writes in response to the write aggregation and de-staging timer. 13 . A memory system comprising: a host interface; a plurality of memory dies; and a memory controller communicatively coupled to the host interface and the plurality of memory dies, the memory controller including logic coupled to one more substrates, wherein the logic is to: determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis, wherein the projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters; and receive, from a host, a requested bandwidth level and a requested quality of service level in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels. 14 . The memory system of claim 13 , wherein the one or more storage device parameters include one or more of a number of dies, an internal queue depth, a media operation speed, a per die read projection, a per die write projection, or a program or erase suspend projection. 15 . The memory system of claim 14 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a command priority in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels; and control the internal queue depth to maintain the requested quality of service level, wherein the internal queue depth is controlled based at least in part on dynamically reallocating the command priority via the memory controller. 16 . The memory system of claim 15 , wherein the logic coupled to the one or more substrates is to: receive, from the host, permission to dynamically reallocate the command priority via the memory controller; receive, from the host, instructions on how to dynamically reallocate the command priority; receive, from the host, a request for a current priority of a first user; and report the current priority of the first user to the host based on the dynamic reallocation of the command priority, wherein the dynamic reallocation of the command priority for a first user includes configuring a first percentage of first user commands to be executed at a first priority and a second percentage of first user commands to be executed at a second priority, and wherein the first priority is different from the second priority, wherein the dynamic reallocation of the command priority is based at least in part on one or more of a change in the internal queue depth, a change in media type among a plurality of storage devices, a change in power management per user, or a change in defragment policy. 17 . The memory system of claim 13 , wherein the logic coupled to the one or more substrates is to: receive, from the host, a request for a change in media type among a plurality of storage devices; select a target storage device from the plurality of storage devices including a first storage device of a first media type and a second storage device of a second media type, wherein the second device is to operate more slowly than the first device; and issue an incoming user command to the target storage device, wherei

Assignees

Inventors

Classifications

  • based on usage prediction · CPC title

  • Centralised allocation of resources · CPC title

  • QOS or priority aware · CPC title

  • H04L47/24Primary

    Traffic characterised by specific attributes, e.g. priority or QoS · CPC title

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What does patent US2021392083A1 cover?
Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality o…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H04L47/24. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).