Defense of jtag i/o network

Patent metadata

Field	Value
Publication number	US-2021391985-A1
Application number	US-202117303648-A
Country	US
Kind code	A1
Filing date	Jun 3, 2021
Priority date	Jun 12, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

An integrated circuit includes, in part, a key management unit configured to generate a seeding key during a start-up phase, an encryption module configured to encrypt data using the seeding key and deliver the encrypted data to a second integrated circuit, and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC. The second integrated circuit includes, in part, a decoder configured to decode the seeding key. Each of the integrated circuits further includes, in part, a linear-feedback shift register that receives the same clock signals and loads the seeding key.

First claim

We claim:

1 . A method for delivering data from a first integrated circuit (IC), the method comprising:
generating a seeding key during a start-up phase of the first IC; encrypting the data using the seeding key to generate encrypted data; encoding the seeding key; delivering the encoded seeding key to a second IC; and delivering the encrypted data to the second IC.

2 . The method of claim 1 further comprising:
loading the seeding key to a linear-feedback shift register disposed in the first IC.

3 . The method of claim 2 further comprising:
decoding the seeding key at the second IC; and
loading the decoded seeding key to a linear-feedback shift register disposed in the second IC.

4 . The method of claim 3 further comprising:
applying a same clock signal to the linear-feedback shift registers disposed in the first and second ICs.

5 . The method of claim 4 further comprising:
decoding the seeding key using a plurality of states of a state machine.

6 . The method of claim 5 wherein said decoding is performed by a Joint Test Action Group (JTAG) block disposed in the second IC.

7 . The method of claim 6 wherein said state machine is disposed in a test access port (TAP) controller of the JTAG block.

8 . The method of claim 7 wherein the data is supplied by a plurality of boundary scan chain cells disposed in the first IC

9 . The method of claim 8 wherein if the decoded seeding key at the second IC fails to match an expected seeding key, a clock signal causing the second IC to lock is applied thereto.

10 . The method of claim 9 wherein said seeding key is generated using a physically unclonable function (PUF) characteristic of the first IC.

11 . A first integrated circuit comprising:
a key management unit configured to generate a seeding key during a start-up phase; an encryption module configured to encrypt received data using the seeding key and deliver the encrypted data to a second integrated circuit (IC); and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC.

12 . The first integrated circuit of claim 11 further comprising:
a linear-feedback shift register configured to store the seeding key.

13 . The first integrated circuit of claim 12 wherein said second IC comprises:
a decoder configured to decode the seeding key; and
a linear-feedback shift register configured to load the decoded seeding key.

14 . The first integrated circuit of claim 13 wherein the linear-feedback shift registers disposed in the first and second ICs receive a same clock signal.

15 . The first integrated circuit of claim 14 wherein the second IC further comprises:
a state machine having a plurality of states decoding the seeding key.

16 . The first integrated circuit of claim 15 wherein said decoder is disposed in a Joint Test Action Group (JTAG) block of the second IC.

17 . The first integrated circuit of claim 16 wherein said state machine is disposed in a test access port (TAP) controller of the JTAG block.

18 . The first integrated circuit of claim 17 further comprising:
a plurality of boundary scan chain cells disposed in the first IC and configured to supply the data.

19 . The first integrated circuit of claim 18 further comprising:
a comparator disposed in the second IC, said comparator configured to cause the second IC to receive a clock signal causing the second IC to lock if the decoded seeding key fails to match an expected key.

20 . The first integrated circuit of claim 19 wherein said seeding key is generated using a physically unclonable function (PUF) characteristic of the first IC.

Assignees

• Univ Florida

Inventors

• Bhunia Swarup
• Vega Christopher
• Paul Shubhra Deb
• Difuntorum Parker
• Dizon Reiner
• Sristi Lakshmiprasanna Sriramakumara Patanjali

Classifications

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• H04L9/0861

  Generation of secret information including derivation or calculation of cryptographic keys or passwords · CPC title

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title