Self biased rectifier circuit

Patent metadata

Field	Value
Publication number	US-2021391804-A1
Application number	US-201917282311-A
Country	US
Kind code	A1
Filing date	Oct 1, 2019
Priority date	Oct 2, 2018
Publication date	Dec 16, 2021
Grant date	—

Abstract

A self-biased rectifier circuit includes first and second input terminals and first and second output terminals. The self-biased rectifier circuit also includes a rectifier having first, second, third, and fourth transistors, each having a source, gate, and drain. The sources of the first and second transistors and the gates of the third and fourth transistors are coupled to the first input terminal. The sources of the third and fourth transistors and the gates of the first and second transistors are coupled to the second input terminal. The drains of the first and third transistors are coupled to the second output terminal. The drains of the second and fourth transistors are coupled to the first output terminal. A feedback circuit includes a plurality of transistors configured as at least one rectifier. The feedback circuit is coupled to the gates of the first and third transistors and the plurality of transistors are configured to provide a first biasing voltage or a second biasing voltage to the gates of the first and third transistors depending upon a magnitude of power or voltage applied to the first and second input terminals. Additionally, or alternatively, the feedback circuit is coupled to the gates of the second and fourth transistors and the plurality of transistors are configured to provide a first biasing voltage or a second biasing voltage to the gates of the second and fourth transistors depending upon a magnitude of power or voltage applied to the first and second input terminals.

First claim

1 . A self-biased rectifier circuit, comprising:
first and second input terminals; first and second output terminals; a rectifier comprising first, second, third, and fourth transistors, each comprising a source, gate, and drain, wherein the sources of the first and second transistors and the gates of the third and fourth transistors are coupled to the first input terminal, the sources of the third and fourth transistors and the gates of the first and second transistors are coupled to the second input terminal, the drains of the first and third transistors are coupled to the second output terminal, and the drains of the second and fourth transistors are coupled to the first output terminal; and a feedback circuit (FB) comprising a plurality of transistors configured as at least one rectifier, wherein the feedback circuit (FB) is coupled to the gates of the first and third transistors and the plurality of transistors are configured to provide a first biasing voltage or a second biasing voltage to the gates of the first and third transistors depending upon a magnitude of power or voltage applied to the first and second input terminals; and/or the feedback circuit (FB) is coupled to the gates of the second and fourth transistors and the plurality of transistors are configured to provide a first biasing voltage or a second biasing voltage to the gates of the second and fourth transistors depending upon a magnitude of power or voltage applied to the first and second input terminals.

2 . The self-biased rectifier circuit of claim 1 , wherein
the first input terminal is coupled to a first node, the second input terminal is coupled to a second node, the first output terminal and the drains of the second and fourth transistors are coupled to a third node, the second output terminal and the drains of the first and third transistors are coupled to a fourth node, the sources of the first and second transistors and the feedback circuit are coupled to a fifth node, a first capacitor is coupled between the fifth node and the first node, the sources of the third and fourth transistors and the feedback circuit are coupled to a sixth node, and a second capacitor is coupled between the sixth node and the second node.

3 . The self-biased rectifier circuit of claim 2 , wherein the feedback circuit comprises one or more feedback circuits, and wherein
one of the one or more feedback circuits is coupled to the gates of the second and fourth transistors and the self-biased rectifier circuit further comprising an eighth capacitor coupled between the first node and the gate of the fourth transistor and a ninth capacitor coupled between the second node and the gate of the second transistor, and/or a second one of the one or more feedback circuits is coupled the gates of the first and third transistors and the self-biased rectifier circuit further comprising a third capacitor coupled between the first node and the gate of the third transistor and a fifth capacitor coupled between the second node and the gate of the first transistor.

4 . The self-biased rectifier circuit of claim 2 , wherein the feedback circuit is coupled to the gates of the second and fourth transistors and to the fourth node, the self-biased rectifier circuit further comprising:
an eighth capacitor coupled between the first node and the gate of the fourth transistor; a seventh capacitor coupled between the feedback circuit and the first node; a ninth capacitor coupled between the second node and the gate of the second transistor; and a tenth capacitor coupled between the second node and the feedback circuit.

5 . The self-biased rectifier circuit of claim 2 , wherein the feedback circuit is coupled to the gates of the first and third transistors and to the third node, the self-biased rectifier circuit further comprising:
a third capacitor coupled between the first node and the gate of the third transistor; a fourth capacitor coupled between the first node and the feedback circuit; a fifth capacitor coupled between the second node and the gate of the first transistor; and a sixth capacitor coupled between the second node and the feedback circuit.

6 . The self-biased rectifier circuit of claim 2 , wherein the feedback circuit comprises a first and second feedback circuit, the first feedback circuit is coupled to the gates of the first and third transistors and to the third node, and the second feedback circuit is coupled to the gates of the second and fourth transistors and to the fourth node, the self-biased rectifier circuit further comprising:
a third capacitor coupled between the first node and the gate of the third transistor; a fourth capacitor coupled between the first node and the first feedback circuit; a fifth capacitor coupled between the second node and the gate of the first transistor; a sixth capacitor coupled between the second node and the first feedback circuit; a seventh capacitor coupled between the first node and the second feedback circuit; an eighth capacitor coupled between the first node and the gate of the fourth transistor; a ninth capacitor coupled between the second node and the gate of the second transistor; and a tenth capacitor coupled between the second node and the second feedback circuit.

7 . The self-biased rectifier circuit of claim 2 , wherein the feedback circuit is coupled to the gates of the first, second, third, and fourth transistors, the self-biased rectifier circuit further comprising:
a third capacitor coupled between the first node and the gate of the third transistor; a fourth capacitor coupled between the first node and the feedback circuit; a fifth capacitor coupled between the second node and the gate of the first transistor; a sixth capacitor coupled between the second node and the feedback circuit; a ninth capacitor coupled between the second node and the gate of the second transistor; and an eighth capacitor coupled between the first node and the gate of the fourth transistor.

8 . The self-biased rectifier circuit of claim 2 , wherein the plurality of transistors of the feedback circuit comprise fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors, each comprising a source, gate, and drain, wherein the fifth, sixth, seventh, and eighth transistors form a first fully cross-coupled rectifier, wherein the ninth, tenth, eleventh, and twelfth transistors form a second fully cross-coupled rectifier, wherein the sources of the fifth, sixth, ninth, and tenth transistors are coupled to the fifth node, and wherein the sources of the seventh, eighth, eleventh, and twelfth transistors are coupled to the sixth node.

9 . The self-biased rectifier circuit of claim 8 , wherein
the gates of the fifth, sixth, ninth, and tenth transistors are coupled to an eighth node, the gates of the seventh, eighth, eleventh, and twelfth transistors are coupled to a ninth node, the drains of the fifth, sixth, seventh, and eighth transistors and the gate of the fourth transistor are coupled to a tenth node, the drains of the ninth, tenth, eleventh, and twelfth transistors and the gate of the second transistor are coupled to a seventh node, and an eighth capacitor is coupled between the first and tenth nodes, a seventh capacitor is coupled between the first and ninth nodes, a ninth capacitor is coupled between the second and seventh nodes, a tenth capacitor is coupled between the second and eighth nodes, and a pair of diode-connected transistors are coupled to the second output terminal and the eighth and ninth nodes.

10 . The self-biased rectifier circuit of claim 8 , wherein
the gates of the fifth and ninth transistors are coupled to an eighth node, the gates

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Salama Khaled Nabil
• Almansouri Abdullah Saud

Classifications

• H02M7/217 Primary

  using semiconductor devices only · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M7/219 Primary

  in a bridge configuration · CPC title