Universal buck-boost topology and switching sequence

Patent metadata

Field	Value
Publication number	US-2021391797-A1
Application number	US-202016930866-A
Country	US
Kind code	A1
Filing date	Jul 16, 2020
Priority date	May 11, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

A buck-boost power converting system includes a voltage source input for connecting a voltage source for power conversion. A plurality of switches are connected electrically to the voltage source input, wherein each switch is connected to a controller configured for control of the switches. A voltage output is configured to connect to a load to power the load with converted power from the voltage source input, wherein the controller is configured to provide positive voltage or negative voltage at a desired level to the voltage output, as needed.

First claim

What is claimed is:

1 . A buck-boost power converting system comprising:
a voltage source input for connecting a voltage source for power conversion; a plurality of switches electrically connected to the voltage source input, wherein each switch is connected to a controller configured for control of the switches; and a voltage output configured to connect to a load to power the load with converted power from the voltage source input, wherein the controller is configured to provide positive voltage or negative voltage to the voltage output, as needed.

2 . The system as recited in claim 1 , further comprising:
a first line running from a positive node of the voltage source input to a first node of the voltage output; and a second line running from a negative node of the voltage source input to a second node of the voltage output, wherein the voltage output is configured to power a load connected between the first and second nodes of the voltage output.

3 . The system as recited in claim 2 , further comprising an inductor connected in series along the first line.

4 . The system as recited in claim 3 , further comprising a capacitor connecting between the first and second lines.

5 . The system as recited in claim 4 , wherein the plurality of switches includes:
a first switch connected in series along the first line between the voltage input and the inductor; a second switch connecting between the first line and the second line, wherein the second switch connects to the first line at a node between the first switch and the inductor; a third switch connecting between the first line and the second line, wherein the third switch connects to the first line at a node between the inductor and the first node of the voltage output; a fourth switch connected in series along the first line between the first node of the voltage output and the third switch; and a fifth switch connected in series along a third line that is in parallel with the first line, wherein the third line connects to the first line at a node between the first switch and the inductor, and at the first node of the voltage output.

6 . The system as recited in claim 5 , wherein the controller includes machine readable instructions configured to cause the controller in a non-inverting mode to cycle the switches between a first state and a second state,
wherein in the first state the first switch is on, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is off, and wherein in the second state the first switch is off, the second switch is on, the third switch is off, the fourth switch is on, and the fifth switch is off.

7 . The system as recited in claim 5 , wherein the controller includes machine readable instructions configured to cause the controller in an inverting mode to cycle the switches between a first state and a second state,
wherein in the first state the first switch is on, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is off, and wherein in the second state the first switch is off, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is on.

8 . The system as recited in claim 1 , wherein the plurality of switches includes a first switch, a second switch, a third switch, a fourth switch, and a fifth switch,
wherein the controller includes machine readable instructions for both a non-inverting mode and an inverting mode, wherein the machine readable instructions are configured to cause the controller in the non-inverting mode to cycle the switches between a first non-inverting state and a second non-inverting state, wherein in the first non-inverting state the first switch is on, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is off, wherein in the second non-inverting state the first switch is off, the second switch is on, the third switch is off, the fourth switch is on, and the fifth switch is off, wherein the machine readable instructions are configured to cause the controller in the inverting mode to cycle the switches between a first inverting state and a second inverting state, wherein in the first inverting state the first switch is on, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is off, and wherein in the second inverting state the first switch is off, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is on.

9 . The system as recited in claim 8 , wherein the controller and switches are configured for pulse width modulation (PWM) control of the switches from state to state.

10 . The system as recited in claim 1 , wherein the voltage source input has a polarity, wherein in the non-inverting mode, the voltage output has the same polarity as the voltage source input, and wherein in the inverting mode, the voltage output as a polarity opposite that of the voltage source input.

11 . The system as recited in claim 10 , wherein the controller is configured to receive input and to switch between the non-inverting mode and the inverting mode based on the input.

12 . A method comprising:
switching a single buck-boost circuit between an non-inverting mode wherein input voltage polarity is not inverted for output to a load, and an inverting mode wherein input voltage polarity is inverted for output to the load.

13 . The method as recited in claim 12 , wherein the buck-boost circuit includes a first switch, a second switch, a third switch, a fourth switch, and a fifth switch, wherein in each of the non-inverting and inverting modes, the method includes pulse width modulation (PWM) control of the switches.

14 . The method as recited in claim 13 , wherein PWM control of the switches includes in the non-inverting mode cycling the switches between a first state and a second state,
wherein in the first state the first switch is on, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is off, and wherein in the second state the first switch is off, the second switch is on, the third switch is off, the fourth switch is on, and the fifth switch is off.

15 . The method as recited in claim 13 , wherein PWM control of the switches includes in the inverting mode cycling the switches between a first state and a second state,
wherein in the first state the first switch is on, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is off, and wherein in the second state the first switch is off, the second switch is off, the third switch is on, the fourth switch is off, and the fifth switch is on.

Assignees

• Hamilton Sundstrand Corp

Inventors

• Somani Vaibhav Kumar
• Yadav Raviprakash

Classifications

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M1/009

  having two or more independently controlled outputs (for DC-DC converter with intermediate AC H02M3/33561) · CPC title

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/0003

  Details of control, feedback or regulation circuits · CPC title