Control circuit with overcurrent prediction to drive capacitive load

Patent metadata

Field	Value
Publication number	US-2021391702-A1
Application number	US-202017080518-A
Country	US
Kind code	A1
Filing date	Oct 26, 2020
Priority date	Jun 15, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

An apparatus includes: an input configured to receive an input voltage; an prediction circuit coupled to the input and configured to provide an overcurrent prediction based on analysis of the input voltage; a delay circuit coupled to the input; a gain control circuit coupled to an output of the delay circuit and configured to selectively adjust a gain applied to at least one frequency range of the input voltage based on the overcurrent prediction; a driver coupled to an output of the gain control circuit; and a capacitive load coupled to an output of the driver.

First claim

What is claimed is:

1 . An apparatus, comprising:
an input configured to receive an input voltage; a prediction circuit coupled to the input and configured to provide an overcurrent prediction voltage based on of the input voltage; a delay circuit coupled to the input; a gain control circuit coupled to an output of the delay circuit and configured to selectively adjust a gain applied to at least one frequency range of the input voltage based on the overcurrent prediction voltage; a driver coupled to an output of the gain control circuit; and a capacitive load coupled to an output of the driver.

2 . The apparatus of claim 1 , in which the prediction circuit is configured to filter the input voltage to obtain first input voltage content associated with a first frequency range and second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range, and wherein the overcurrent prediction is based on analysis of the first input content.

3 . The apparatus of claim 1 , in which the delay circuit includes:
a delay buffer; a low-pass filter coupled to an output of the delay buffer; and a high-pass filter coupled to the output of the delay buffer.

4 . The apparatus of claim 1 , in which the gain control circuit includes:
a first multiplier coupled to an output of the low-pass filter; a second multiplier coupled to an output of the high-pass filter; and a summation circuit coupled to outputs of the first and second multipliers.

5 . The apparatus of claim 4 , in which the prediction circuit includes:
a low-pass filter coupled to the input; a first feedback loop coupled to an output of the low-pass filter; a high-pass filter coupled to the input; a second feedback loop coupled to an output of the high-pass filter; and a weight selection controller coupled to the first and second feedback loops.

6 . The apparatus of claim 5 , in which the first feedback loop includes:
a third multiplier block; a first attack/decay block coupled to the third multiplier block; a first smooth block coupled to the first attach/decay block; and a first minimum block coupled to the first smooth block, wherein an output of the first minimum block is provided to the third multiplier block and to the first multiplier block of the gain control circuit, and wherein the second feedback loop includes:
a fourth multiplier block;
a second attack/decay block coupled to the fourth multiplier block;
a second smooth block coupled to the second attack/decay block; and
a second minimum block coupled to the second smooth block, wherein an output of the second minimum block is provided to fourth multiplier block and to the second multiplier block of the gain control circuit.

7 . The apparatus of claim 6 , in which the weight selection controller includes:
a summation block; a voltage-to-current transfer function block coupled to the summation block; a third attack/decay block coupled to the voltage-to-current transfer function block; a third smooth block coupled to the third attach/decay block; a first weight block coupled to the third smooth block, wherein an output of the first weight block is provided to the first minimum block; and a second weight block coupled to the third smooth block, wherein an output of the second weight block is provided to the second minimum block.

8 . The apparatus of claim 1 , including a display, in which the capacitive load is a piezo speaker mechanically coupled to the display.

9 . The apparatus of claim 1 , in which the input, the prediction circuit, the delay circuit, and the gain control circuit are components of an integrated circuit.

10 . The apparatus of claim 1 , in which operations of the prediction circuit, the delay circuit, and the gain control circuit are performed by a digital signal processor (DSP).

11 . An integrated circuit, comprising:
an input configured to receive an input voltage; and a control circuit coupled to the input and configured to:
delay the input voltage;
provide an overcurrent prediction voltage while the input voltage is delayed, in which the overcurrent prediction voltage is based on the input voltage and an impedance network profile;
select a gain for at least one frequency range of the input voltage based on the overcurrent prediction voltage; and
output a drive voltage to a capacitive load based on the selected gain.

12 . The integrated circuit of claim 11 , in which the control circuit is configured to filter the input voltage to obtain low-frequency content and high-frequency content, and wherein the overcurrent prediction voltage is based on analysis of the high-frequency content.

13 . The integrated circuit of claim 11 , in which the control circuit is further configured to:
store the input voltage; filter the input voltage to obtain low-frequency content and high-frequency content; multiply the high-frequency content by a first gain to obtain adjusted high-frequency content, wherein the first gain is based on the overcurrent prediction voltage; multiply the low-frequency content by a second gain to obtain adjusted low-frequency content; and combine the adjusted low-frequency content and the adjusted high-frequency content.

14 . The integrated circuit of claim 13 , in which the control circuit is further configured to:
filter the input voltage to obtain low-frequency content and high-frequency content; apply a first feedback loop to the high-frequency content to generate the first gain; and apply a second feedback loop to the low-frequency content to generate the second gain.

15 . The integrated circuit of claim 14 , in which the control circuit is further configured to apply weights to the first gain and the second gain based on weight selection operations that account for the high-frequency content and the low-frequency content.

16 . A method, comprising:
delaying an input voltage; providing an overcurrent prediction while the input voltage is delayed, where the overcurrent prediction is based on analysis of the input voltage and a capacitive load profile; selecting a gain for at least one frequency range of the input voltage based on the overcurrent prediction voltage; and outputting a drive voltage to a capacitive load based on the selected gain.

17 . The method of claim 16 , including filtering the input voltage to obtain first input voltage content associated with a first frequency range and second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range, and wherein the overcurrent prediction is based on the first input voltage content.

18 . The method of claim 16 , including:
storing the input voltage; filtering the input voltage to obtain first input voltage content associated with a first frequency range and second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range; multiplying the first input voltage content by a first gain to obtain adjusted first input voltage content, wherein the first gain is based on the overcurrent prediction voltage; multiplying the second input voltage content by a second gain to obtain adjusted second input voltage content; and combining the adjusted first input voltage content and the adjusted second input voltage content.

19 . The method of claim 18 , including:
filtering the input voltage to obtain fir

Assignees

• Texas Instruments Inc

Inventors

• Yang Yuqing
• Cao Hua
• Wan Yurong
• Qin Xiaolin
• Shen Weiyu

Classifications

• H04R2499/15

  Transducers incorporated in visual displaying devices, e.g. televisions, computer displays, laptops · CPC title

• H04R17/00

  Piezoelectric transducers; Electrostrictive transducers (piezoelectric or electrostrictive elements in general H10N30/00; details of piezoelectric or electrostrictive motors, generators or positioners {H10N30/00}) · CPC title

• H04R3/007 Primary

  Protection circuits for transducers · CPC title

• H02H9/02

  responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)} · CPC title

• H02H1/0007 Primary

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title