Semiconductor device, method of manufacturing semiconductor device, and imaging element

Patent metadata

Field	Value
Publication number	US-2021391369-A1
Application number	US-201917279962-A
Country	US
Kind code	A1
Filing date	Sep 17, 2019
Priority date	Oct 5, 2018
Publication date	Dec 16, 2021
Grant date	—

Abstract

To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device includes: a first semiconductor substrate; and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.

First claim

1 . A semiconductor device comprising:
a first semiconductor substrate that is provided with a first electrode including a first protruding portion and a first base portion, the first protruding portion including a first abutting surface, the first base portion being linked to the first protruding portion and having volume greater than volume of the first protruding portion; and a second semiconductor substrate that is provided with a second electrode including a second protruding portion and a second base portion, the second protruding portion including a second abutting surface that abuts the first abutting surface, the second base portion being linked to the second protruding portion and having volume greater than volume of the second protruding portion, the second semiconductor substrate being stacked on the first semiconductor substrate.

2 . The semiconductor device according to claim 1 , wherein area occupied by the first base portion is greater than area occupied by the first protruding portion in a plane orthogonal to a stack direction of the first semiconductor substrate and the second semiconductor substrate.

3 . The semiconductor device according to claim 2 , wherein area occupied by the second base portion is greater than area occupied by the second protruding portion in the plane orthogonal to the stack direction.

4 . The semiconductor device according to claim 1 , wherein
the first semiconductor substrate includes a pixel region in which a plurality of imaging elements is formed and a peripheral region that surrounds the pixel region, and abutting sections of the first abutting surface and the second abutting surface are formed in a region that overlaps with the pixel region in a stack direction of the first semiconductor substrate and the second semiconductor substrate.

5 . The semiconductor device according to claim 1 , wherein the first abutting surface and the second abutting surface form abutting sections that are joined together by using plasma junction.

6 . The semiconductor device according to claim 1 , wherein the second electrode includes a plurality of the second protruding portions linked to the one second base portion.

7 . The semiconductor device according to claim 1 , further comprising:
a first barrier layer that surrounds the first electrode in an in-plane direction orthogonal to a stack direction of the first semiconductor substrate and the second semiconductor substrate; and a second barrier layer that surrounds the second electrode in the in-plane direction.

8 . A method of manufacturing a semiconductor device, the method comprising:
polishing a first abutting surface after a first semiconductor substrate is prepared, the first semiconductor substrate being provided with a first electrode including a first protruding portion and a first base portion, the first protruding portion including the first abutting surface, the first base portion being linked to the first protruding portion and having volume greater than volume of the first protruding portion; polishing a second abutting surface after a second semiconductor substrate is prepared, the second semiconductor substrate being provided with a second electrode including a second protruding portion and a second base portion, the second protruding portion including the second abutting surface, the second base portion being linked to the second protruding portion and having volume greater than volume of the second protruding portion; superimposing the second semiconductor substrate on the first semiconductor substrate and joining the second semiconductor substrate to the first semiconductor substrate to cause the polished first abutting surface and the polished second abutting surface to be opposed to each other; and electrically coupling the first protruding portion and the second protruding portion by heating the first semiconductor substrate and the second semiconductor substrate that have been joined together.

9 . An imaging element comprising:
a first semiconductor substrate including a photoelectric conversion section and a first electrode; and a second semiconductor substrate that is stacked on the first semiconductor substrate, the second semiconductor substrate including a logic circuit and a second electrode, wherein the first electrode includes a first portion and a second portion, the second portion being adjacent to the first portion in a stack direction of the first semiconductor substrate and the second semiconductor substrate, the second electrode includes a third portion and a fourth portion, the third portion being joined to the first portion, the fourth portion being adjacent to the third portion in the stack direction, a first width of the first portion in an in-plane direction orthogonal to the stack direction is smaller than a second width of the second portion in the in-plane direction, and a third width of the third portion in the in-plane direction is smaller than a fourth width of the fourth portion in the in-plane direction.

10 . The imaging element according to claim 9 , wherein
the first semiconductor substrate further includes a third electrode that is disposed adjacent to the first electrode in the in-plane direction, the third electrode includes a fifth portion and a sixth portion, the sixth portion being adjacent to the fifth portion in the stack direction, a fifth width of the fifth portion in the in-plane direction is smaller than a sixth width of the sixth portion in the in-plane direction, and a first distance between the first portion and the fifth portion is equal to or greater than a second distance between the second portion and the sixth portion.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Hagimoto Yoshiya
• Fujii Nobutoshi

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/732

  having shape changed during the connecting · CPC title

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title