SiC WAFER MANUFACTURING METHOD

Patent metadata

Field	Value
Publication number	US-2021375613-A1
Application number	US-201917262387-A
Country	US
Kind code	A1
Filing date	Jul 25, 2019
Priority date	Jul 25, 2018
Publication date	Dec 2, 2021
Grant date	—

Abstract

In a method for manufacturing an SiC wafer, a work-affected layer removal step of removing a work-affected layer generated in a surface and inside of an SiC wafer is performed, so that the SiC wafer from which the work-affected layer is at least partially removed is manufactured. In the work-affected layer removal step, the SiC wafer having undergone a polishing step is etched with an etching amount of 10 μm or less by being heated under Si vapor pressure so that the work-affected layer is removed. In the polishing step, an oxidizer is used to produce a reaction product in the SiC wafer while abrasive grains are used to remove the reaction product. In the SiC wafer having undergone the polishing step, an internal stress caused by the work-affected layer is present at a location inner than the work-affected layer, and an internal stress of the SiC wafer is reduced by removing the work-affected layer in the work-affected layer removal step.

First claim

1 . A method for manufacturing an SiC wafer from which a work-affected layer is removed, the method comprising a work-affected layer removal step of removing a work-affected layer generated in a surface and inside of an SiC wafer, to manufacture an SiC wafer from which the work-affected layer is at least partially removed, wherein
in the work-affected layer removal step, a post-polishing wafer is etched with an etching amount of 10 μm or less by being heated under Si vapor pressure so that the work-affected layer is removed, the post-polishing wafer being a wafer whose surface has been polished by using an oxidizer to produce a reaction product in the SiC wafer while using abrasive grains to remove the reaction product, and in the post-polishing wafer, a stress caused by the work-affected layer is present at a location inner than the work-affected layer, and an internal stress of the SiC wafer is reduced by removing the work-affected layer in the work-affected layer removal step.

2 . The method according to claim 1 for manufacturing an SiC wafer from which a work-affected layer is removed, wherein
the surface of the post-polishing wafer has an arithmetic surface roughness (Ra) of 0.7 nm or less.

3 . The method according to claim 1 for manufacturing an SiC wafer from which a work-affected layer is removed, wherein
in the work-affected layer removal step, the etching is performed with an etching amount of 20 nm or more.

4 . The method according to claim 1 for manufacturing an SiC wafer from which a work-affected layer is removed, the method further comprising a polishing step that is performed before the work-affected layer removal step, wherein
in the polishing step, the oxidizer is used to produce the reaction product in the SiC wafer while the abrasive grains are used to remove the reaction product, so that a surface is polished.

5 . The method according to claim 4 for manufacturing an SiC wafer from which a work-affected layer is removed, wherein
in the polishing step, the abrasive grains having a lower hardness than SiC are used for polishing.

Assignees

• Toyo Tanso Co

Inventors

• Yabuki Norihito
• Nakashima Yuji
• Sakaguchi Takuya
• Nogami Satoru
• Kitabatake Makoto

Classifications

• H10P90/123

  by grinding or lapping · CPC title

• H10P90/126 Primary

  by chemical etching · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• B24B7/228

  for grinding thin, brittle parts, e.g. semiconductors, wafers (grinding edges of thin, brittle parts B24B9/065) · CPC title