Display device

Patent metadata

Field	Value
Publication number	US-2021375178-A1
Application number	US-202117443240-A
Country	US
Kind code	A1
Filing date	Jul 22, 2021
Priority date	Jun 16, 2020
Publication date	Dec 2, 2021
Grant date	—

Abstract

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge of the start signal within the vertical blanking cycle of the (N−1) th frame cycle. Alternatively, the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N th frame cycle.

First claim

What is claimed is:

1 . A display device, comprising:
a plurality of scanning lines; a gate driver circuit electrically connected to the plurality of scanning lines; and a timing controller electrically connected to the gate driver circuit; wherein the timing controller is configured to: receive a plurality of data enable signals within each frame cycle of a plurality of frame cycles, generate a gate control signal according to the plurality of data enable signals, and provide the gate control signal for the gate driver circuit; wherein the gate driver circuit is configured to provide scanning signals for the plurality of scanning lines according to the gate control signal; wherein the gate control signal comprises a start signal, a first clock signal and a second clock signal; wherein each frame cycle comprises an active cycle and a vertical blanking cycle, and the plurality of data enable signals are only within the active cycle; and wherein the timing controller is configured to generate a rising edge of the start signal within the vertical blanking cycle of an (N−1) th frame cycle, wherein a time interval between a falling edge of a last data enable signal in the (N−1) th frame cycle and the rising edge of the start signal is T, wherein T is greater than 0 and less than a first preset time interval, or T is greater than 0 and equal to a first preset time interval, wherein the first preset time interval is less than

2
3

of the vertical blanking cycle; or, wherein the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval defined by a rising edge and a falling edge of a first data enable signal in an N th frame cycle;
wherein N≥2.

2 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge of the start signal within the vertical blanking cycle of the (N−1) th frame cycle, the rising edge of the start signal is generated after the falling edge of the last data enable signal in the (N−1) th frame cycle.

3 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge of the start signal within the vertical blanking cycle of the (N−1) th frame cycle, a falling edge of the start signal is generated within the vertical blanking cycle of the (N−1) th frame cycle.

4 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge of the start signal within the vertical blanking cycle of the (N−1) th frame cycle, a falling edge of the start signal is generated within a time interval formed by a rising edge and a falling edge of a first data enable signal in an N th frame cycle.

5 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge of the start signal within the vertical blanking cycle of the (N−1) th frame cycle, P second clock signals are generated within the (N−1) th frame cycle; and
wherein a time interval between the falling edge of the last data enable signal in the (N−1) th frame cycle and a falling edge of a (P−1) th second clock signal among the P second clock signals is (T−start), wherein T is greater than (T−start), and P≥2.

6 . The display device of claim 1 , wherein when where the timing controller is configured to generate the rising edge of the start signal within the vertical blanking cycle of the (N−1) th frame cycle, a falling edge of a 1 st first clock signal in an N th frame cycle is generated when a falling edge of a first data enable signal in the N th frame cycle is generated, wherein a rising edge of the 1 st first clock signal in the N th frame cycle is generated within a time interval defined by a falling edge of the start signal and a rising edge of the first data enable signal in the N th frame cycle.

7 . The display device of claim 1 , wherein the first preset time interval is less than half of the vertical blanking cycle.

8 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the rising edge of the start signal is generated when the rising edge of the first data enable signal in the N th frame cycle is generated.

9 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the rising edge of the start signal is generated after the rising edge of the first data enable signal in the N th frame cycle.

10 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, a rising edge and a falling edge of the first clock signal are generated within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle.

11 . The display device of claim 10 , wherein within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the rising edge of the first clock signal is generated after a falling edge of the second clock signal.

12 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the falling edge of the start signal is generated before a rising edge of the first clock signal, or the falling edge of the start signal is generated when a rising edge of the first clock signal is generated.

13 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the falling edge of the start signal is generated after a rising edge of the first clock signal, or the falling edge of the start signal is generated when a rising edge of the first clock signal is generated.

14 . The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, a width of the first clock signal generated within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle is less than a width of the first clock signal generated outside the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, and a width of the second

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Luo Sijian
• Wu Changzhi
• Xu Yumin

Classifications

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title