Shift register unit, scan driving circuit, array substrate, display device, and driving method

Patent metadata

Field	Value
Publication number	US-2021358356-A1
Application number	US-201816315904-A
Country	US
Kind code	A1
Filing date	Mar 12, 2018
Priority date	Jul 17, 2017
Publication date	Nov 18, 2021
Grant date	—

Abstract

A shift register unit, a scan driving circuit, an array substrate, a display device, and a driving method are provided. The shift register unit includes an input circuit, a replacement circuit, an output circuit, and a pull-down circuit; the input circuit is respectively connected to the input terminal and the first node, and is configured to set the first node to an active level when the input terminal (IN) is at an active level; the replacement circuit is respectively connected to the input terminal and the second node, and is configured to set the second node to an inactive level when the input terminal is at an active level.

First claim

1 . A shift register unit, comprising an input terminal, an output terminal, an input circuit, a replacement circuit, an output circuit, and a pull-down circuit;
wherein the input circuit is respectively connected to the input terminal and a first node, and is configured to set the first node to an active level of the first node when the input terminal is at an active level of the input terminal; the replacement circuit is respectively connected to the input terminal and a second node, and is configured to set the second node to an inactive level of the second node when the input terminal is at the active level of the input terminal; the output circuit is respectively connected to the first node and the output terminal, and is configured to set the output terminal to an active level of the output terminal by using a clock signal when the first node is at the active level of the first node; and the pull-down circuit is respectively connected to the first node, the output terminal, and the second node, and is configured to set the first node to an inactive level of the first node and the output terminal to an inactive level of the output terminal when the second node is at an active level of the second node.

2 . The shift register unit according to claim 1 , wherein the replacement circuit comprises a first transistor;
a gate electrode of the first transistor is connected to the input terminal, a first electrode of the first transistor is connected to the second node, and a second electrode of the first transistor is connected for the inactive level of the second node.

3 . The shift register unit according to claim 1 , further comprising a pull-down control circuit,
wherein the pull-down control circuit is respectively connected to the first node and the second node, and is configured to set the second node to the inactive level of the second node when the first node is at the active level, and use the clock signal to set the second node to the active level when the first node is at the inactive level of the first node.

4 . The shift register unit according to claim 3 , further comprising a reset terminal and a reset circuit,
wherein the reset circuit is respectively connected to the reset terminal, and the first node and the output terminal, and is configured to set the first node to an inactive level of the first node and the output terminal to an inactive level of the output terminal when the reset terminal is at an active level of the reset terminal.

5 . The shift register unit according to claim 1 , wherein the input circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the input terminal, a first electrode of the second transistor is connected to the input terminal or connected for the active level of the first node, and a second electrode of the second transistor is connected to the first node.

6 . The shift register unit according to claim 1 , wherein the output circuit comprises a third transistor and a first capacitor,
a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a first clock signal line, and a second electrode of the third transistor is connected to the output terminal; and a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the output terminal.

7 . The shift register unit according to claim 4 , wherein the reset circuit comprises a fourth transistor and a fifth transistor,
a gate electrode of the fourth transistor is connected to the reset terminal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected for the inactive level of the first node; and a gate electrode of the fifth transistor is connected to the reset terminal, a first electrode of the fifth transistor is connected to the output terminal, and a second electrode of the fifth transistor is connected for the inactive level of the output terminal.

8 . The shift register unit according to claim 1 , wherein the pull-down circuit comprises a sixth transistor and a seventh transistor,
a gate electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected for the inactive level of the first node; and a gate electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the output terminal, and a second electrode of the seventh transistor is connected for the inactive level of the output terminal.

9 . The shift register unit according to claim 3 , wherein the pull-down control circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
a gate electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the second node, and a second electrode of the eighth transistor is connected for the inactive level of the second node; a gate electrode of the ninth transistor is connected to a third node, a first electrode of the ninth transistor is connected to a second clock signal line, and a second electrode of the ninth transistor is connected to the second node; a gate electrode of the tenth transistor is connected to the first node, a first electrode of the tenth transistor is connected to the third node, and a second electrode of the tenth transistor is connected for the inactive level of the second node; and a gate electrode of the eleventh transistor is connected to the second clock signal line, a first electrode of the eleventh transistor is connected to the second clock signal line, and a second electrode of the eleventh transistor is connected to the third node.

10 . The shift register unit according to claim 4 , wherein the input circuit comprises a second transistor, the output circuit comprises a third transistor and a first capacitor, the reset circuit comprises a fourth transistor and a fifth transistor, the pull-down circuit comprises a sixth transistor and a seventh transistor, and the pull-down control circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
wherein a gate electrode of the second transistor is connected to the input terminal, a first electrode of the second transistor is connected to the input terminal or connected for the active level of the first node, and a second electrode of the second transistor is connected to the first node; a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a first clock signal line, and a second electrode of the third transistor is connected to the output terminal; a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the output terminal; a gate electrode of the fourth transistor is connected to the reset terminal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected for the inactive level of the first node; a gate electrode of the fifth transistor is connected to the reset terminal, a first electrode of the fifth transistor is connected to the output terminal, and a second electrode of the fifth transistor is connected for the inactive level of the output terminal; a gate electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xiao Lijun
• Qian Qian
• Gao Shaohong
• Zhou Tao
• Ji Chuan

Classifications

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title