Signal integrity simulation method for encryption hybrid model

Patent metadata

Field	Value
Publication number	US-2021357563-A1
Application number	US-201816493266-A
Country	US
Kind code	A1
Filing date	Oct 26, 2018
Priority date	May 23, 2018
Publication date	Nov 18, 2021
Grant date	—

Abstract

A signal integrity simulation method for an encryption hybrid model is provided. A step response data of a SPICE model is extracted through a transient simulation. An external random code signal is generated. The extracted step response data is imported as an input source for an ADS channel simulator. An eye diagram at a RX end is calculated by the ADS channel simulator based on an algorithm and the external random code signal, to perform measurement on the eye diagram. With the signal integrity simulation method for an encryption hybrid model such as an IBIS AMI model, the problem that signal integration simulation cannot be accurately performed or cannot be performed because models provided by the manufacturer are encrypted or the types of models provided by the manufacturer are not consistent can be effectively solved.

First claim

1 . A signal integrity simulation method for an encryption hybrid model, comprising:
extracting a step response data of a SPICE model through a transient simulation; generating an external random code signal; importing the extracted step response data as an input source of an ADS channel simulator; and calculating, by the ADS channel simulator, an eye diagram at a RX end based on an algorithm and the external random code signal, to perform measurement on the eye diagram.

2 . The signal integrity simulation method for an encryption hybrid model according to claim 1 , wherein
a verification link is formed before performing the transient simulation, and the verification link is formed by connecting a TX end to the RX end via a wiring model, and wherein a chip at the TX end is a SPICE model that is encrypted, and a step response generated by the chip at the TX end comprises all characteristics of the chip at the TX end, and a chip at the RX end is an IBIS AMI model, and the SPICE model at the TX end is a RC circuit.

3 . The signal integrity simulation method for an encryption hybrid model according to claim 1 , wherein in a case that the SPICE model at the TX end is not encrypted, the simulation method comprises the following steps of:
1) importing the SPICE model based on a Spice Wizard function of ADS, wherein the SPICE model at the TX end that is not encrypted is capable of being directly called by the ADS; and reserving an input interface for the SPICE model, to input a step signal outside the SPICE model; 2) establishing a link model; 3) performing a transient step response simulation, wherein the imported SPICE model is connected to a wiring model, and a resistor of 50 ohm is joined at an end of the verification link; inputting an ideal step signal at the input interface reserved for the SPICE model, wherein a simulation time is set to make an output of the step response be in a steady state, and a simulation time interval is set to guarantee calculation accuracy; and extracting the step response data at a position where the resistor is joined, wherein the step response data comprises the characteristics of the chip at the TX end and the verification link; 4) performing a channel simulation, wherein the step response data obtained in step 3) is imported into the channel simulation as a signal source at the RX end, and the external random code signal is inputted, and parameters related to the channel simulation are set; and 5) verifying simulation results, wherein a channel simulation result obtained in step 4) is compared with a transient simulation result, to verify consistency between the channel simulation result and the transient simulation result.

4 . The signal integrity simulation method for an encryption hybrid model according to claim 1 , wherein in a case that the SPICE model at the TX end is encrypted, the simulation method comprises the following steps of:
1) performing a transient simulation based on HSPICE, wherein a transient step response simulation is performed on the encrypted SPICE model and the verification link to obtain a step response output file with a suffix of .lis; and editing a format of the step response output file to form a file with a suffix of .tim that is capable of being called by ADS; 2) performing an active simulation, wherein the step response data (.tim) is imported into the ADS for the active simulation, and wherein the active simulation is performed by calling the step response data in the ADS based on the external random code signal; and 3) verifying simulation results, wherein a transient simulation result is compared with an active simulation result obtained in step 2) to verify consistency between the transient simulation result and the active simulation result.

5 . The signal integrity simulation method for an encryption hybrid model according to claim 2 , wherein in a case that the SPICE model at the TX end is not encrypted, the simulation method comprises the following steps of:
1) importing the SPICE model based on a Spice Wizard function of ADS, wherein the SPICE model at the TX end that is not encrypted is capable of being directly called by the ADS; and reserving an input interface for the SPICE model, to input a step signal outside the SPICE model; 2) establishing a link model; 3) performing a transient step response simulation, wherein the imported SPICE model is connected to the wiring model, and a resistor of 50 ohm is joined at an end of the verification link; inputting an ideal step signal at the input interface reserved for the SPICE model, wherein a simulation time is set to make an output of the step response be in a steady state, and a simulation time interval is set to guarantee calculation accuracy; and extracting the step response data at a position where the resistor is joined, wherein the step response data comprises the characteristics of the chip at the TX end and the verification link; 4) performing a channel simulation, wherein the step response data obtained in step 3) is imported into the channel simulation as a signal source at the RX end, and the external random code signal is inputted, and parameters related to the channel simulation are set; and 5) verifying simulation results, wherein a channel simulation result obtained in step 4) is compared with a transient simulation result, to verify consistency between the channel simulation result and the transient simulation result.

6 . The signal integrity simulation method for an encryption hybrid model according to claim 2 , wherein in a case that the SPICE model at the TX end is encrypted, the simulation method comprises the following steps of:
1) performing a transient simulation based on HSPICE, wherein a transient step response simulation is performed on the encrypted SPICE model and the verification link to obtain a step response output file with a suffix of .lis; and editing a format of the step response output file to form a file with a suffix of .tim that is capable of being called by ADS; 2) performing an active simulation, wherein the step response data (.tim) is imported into the ADS for the active simulation, and wherein the active simulation is performed by calling the step response data in the ADS based on the external random code signal; and 3) verifying simulation results, wherein a transient simulation result is compared with an active simulation result obtained in step 2) to verify consistency between the transient simulation result and the active simulation result.

Assignees

• Zhengzhou Yunhai Information Tech Co Ltd

Inventors

• Rong Shili
• Wang Lin

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/3308

  using simulation · CPC title

• G06F30/31

  Design entry, e.g. editors specifically adapted for circuit design · CPC title