Adaptive folding for integrated memory assembly

Patent metadata

Field	Value
Publication number	US-2021349778-A1
Application number	US-202016870930-A
Country	US
Kind code	A1
Filing date	May 9, 2020
Priority date	May 9, 2020
Publication date	Nov 11, 2021
Grant date	—

Abstract

A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as single bit per memory cell data to increase the performance of the programming process. Subsequently, the control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data.

First claim

We claim:

1 . An apparatus, comprising:
a first semiconductor die comprising non-volatile memory cells and a first plurality of pathways; and a second semiconductor die comprising one or more control circuits, an interface to an off die circuit and a second plurality of pathways, the one or more control circuits are configured to transfer signals through pathway pairs of the first plurality of pathways and the second plurality of pathways, the one or more control circuits are configured to:
read a first set of data as single bit per memory cell data from the first semiconductor die;
on the second semiconductor die, determine a measure of error for the first set of data;
program the first set of data as multiple bit per memory cell data without decoding and re-encoding the first data if the measure of error is less than a first threshold; and
decode the first set of data on the second semiconductor die, re-encode the decoded first set of data on the second semiconductor die and program the re-encoded first set of data as multiple bit per memory cell data if the measure of error is greater than the first threshold.

2 . The apparatus of claim 1 , wherein the one or more control circuits on the second semiconductor die are configured to, if the measure of error is greater than a second threshold, transmit the first set of data to the off die circuit by way of the interface to decode the first set of data at the off die circuit, the second threshold is greater than the first threshold.

3 . The apparatus of claim 2 , further comprising:
a memory controller separate from the first semiconductor die and the second semiconductor die, the memory controller is the off die circuit, the memory controller is connected to the second semiconductor die by a communication channel, the memory controller is configured to decode codewords at a first resolution and first power level, the one or more control circuits on the second semiconductor die are configured to decode codewords at a second resolution that is lower than the first resolution and at a second power level that is lower than the first power level.

4 . The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to read a second set of data as single bit per memory cell data from the first semiconductor die and program the second set of data from the second semiconductor die to a target set of non-volatile memory cells on the first semiconductor die as multiple bit per memory cell data with the first set of data such that multiple memory cells of the target set of non-volatile memory cells store data from both of the first set of data and the second set of data.

5 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
read a second set of data as single bit per memory cell data from the first semiconductor die; read a third set of data as single bit per memory cell data from the first semiconductor die; and program the second set of data and the third set of data from the second semiconductor die to a target set of non-volatile memory cells on the first semiconductor die as multiple bit per memory cell data with the first set of data such that multiple memory cells of the target set of non-volatile memory cells store data from the first set of data, the second set of data and the third set of data.

6 . The apparatus of claim 1 , wherein:
the measure of error is a syndrome weight.

7 . The apparatus of claim 1 , wherein:
the one or more control circuits are configured to determine the measure of error for the first set of data without decoding the first set of data.

8 . The apparatus of claim 1 , wherein:
the first semiconductor die is directly bonded to the second semiconductor die.

9 . The apparatus of claim 1 , further comprising:
a third semiconductor die, the third semiconductor die comprises non-volatile memory cells, the one or more control circuits are further configured to read a second set of data as single bit per memory cell data from the third semiconductor die and program the second set of data from the second semiconductor die to a set of target non-volatile memory cells on the first semiconductor die as multiple bit per memory cell data with the first set of data such that multiple memory cells of the target set of non-volatile memory cells store data from both of the first set of data and the second set of data.

10 . The apparatus of claim 1 , further comprising:
a third semiconductor die, the third semiconductor die comprises non-volatile memory cells, the one or more control circuits are further configured to:
read a second set of data as single bit per memory cell data from the first semiconductor die;
read a third set of data as single bit per memory cell data from the first semiconductor die; and
program the second set of data and the third set of data from the second semiconductor die to a target set of non-volatile memory cells on the third semiconductor die as multiple bit per memory cell data such that multiple memory cells of the target set of non-volatile memory cells store data from the first set of data, the second set of data and the third set of data.

11 . The apparatus of claim 1 , further comprising:
a third semiconductor die, the third semiconductor die comprises non-volatile memory cells and a third plurality of pathways; and a fourth semiconductor die comprising a fourth plurality of pathways and an interface to the second semiconductor die, the fourth semiconductor die is configured to transfer signals through pathway pairs of the third plurality of pathways and the fourth plurality of pathways; the second semiconductor die is configured to read a second set of data as single bit per memory cell data from the first semiconductor die and transfer the second set of data to the fourth semiconductor die; and the fourth semiconductor die is configured to program the second set of data from the fourth semiconductor die to a target set of non-volatile memory cells on the third semiconductor die as multiple bit per memory cell data.

12 . The apparatus of claim 1 , wherein:
the first semiconductor die includes a non-volatile memory array; and the second semiconductor die includes sense amplifiers for reading data from the non-volatile memory array on the first semiconductor die.

13 . The apparatus of claim 12 , wherein:
the non-volatile memory array includes word lines; the second semiconductor die includes address decoders for the non-volatile memory array on the first semiconductor die; and the second semiconductor die includes signal generators configured to generate voltages applied to the word lines of the non-volatile memory array on the first semiconductor die.

14 . The apparatus of claim 1 , wherein:
the first set of data comprises data bits and parity bits; and the one or more control circuits are configured to read the first set of data from the first semiconductor die by reading each data bit and parity bit by way of a different pathway pair of the plurality of pathways.

15 . A method, comprising:
reading a first set of data from a first set of non-volatile memory cells on a memory die that is bonded to a control die, the first set of data is stored as single bit per memory cell data in the first set of non-volatile memory cells; reading a second set of data from a second set of non-volatile memory cells on the memory die, the second set of data is stored as single bit per memory cell data in the second set of non-volatile memory cells; on the control die, determining a measure of error i

Assignees

• Western Digital Tech Inc

Inventors

• Sharon Eran
• Bazarsky Alex
• Alrod Idan

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title