Display panel and display device

Patent metadata

Field	Value
Publication number	US-2021294382-A1
Application number	US-202117338785-A
Country	US
Kind code	A1
Filing date	Jun 4, 2021
Priority date	Aug 27, 2019
Publication date	Sep 23, 2021
Grant date	—

Abstract

A display panel and a display device are provided. The display panel includes first display region and second display region at least partially surrounding the first display region. In the first display region, along a row direction, the first pixel unit in the first pixel unit row is between two adjacent second pixel units in the second pixel unit row, and the second pixel unit in the second pixel unit row is between two adjacent first pixel units in the first pixel unit row. The first pixel circuit and the second pixel circuit are connected to a same first or second signal line. The first pixel unit connected to the first pixel circuit and the second pixel unit connected to the second pixel circuit are located in adjacent rows or columns.

First claim

What is claimed is:

1 . A display panel, comprising:
a display region; and a non-display region; wherein the display region comprises a plurality of pixel units arranged in an array of rows extending along a row direction and of columns extending along a column direction; wherein the display region comprises a first display region and a second display region at least partially surrounding the first display region; wherein the plurality of pixel units comprises a plurality of first pixel unit rows and a plurality of second pixel unit rows that are alternately arranged along the column direction and located in the first display region; each of the plurality of first pixel unit rows comprises a plurality of first pixel units arranged along the row direction, and each of the plurality of second pixel unit rows comprises a plurality of second pixel units arranged along the row direction; along the row direction, in the first pixel unit row, at least one of the plurality of first pixel units is located between two adjacent second pixel units of the plurality of second pixel units of an adjacent second pixel unit row of the plurality of second pixel unit rows, and in the second pixel unit row, at least one of the plurality of second pixel units is located between two adjacent first pixel units of the plurality of first pixel units of an adjacent first pixel unit row of the plurality of first pixel unit rows; wherein the first display region further comprises a plurality of first signal lines extending along the row direction and arranged along the column direction, and a plurality of second signal lines extending along the column direction and arranged along the row direction; wherein the plurality of first signal lines and the plurality of second signal lines intersect to define a plurality of first pixel circuits and a plurality of second pixel circuits, each of the plurality of first pixel circuits is electrically connected to one of the plurality of first pixel units, and each of the plurality of second pixel circuits is electrically connected to one of the plurality of second pixel units; and wherein; at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel circuits are electrically connected to a same first signal line of the plurality of first signal lines and to different second signal lines of the plurality of second signal lines, and at least one of the plurality of first pixel units electrically connected to the at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel units electrically connected to the at least one of the plurality of second pixel circuits are located in adjacent rows of the array; or, at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel circuits are electrically connected to a same second signal line of the plurality of second signal lines and to different first signal lines of the plurality of first signal lines, and at least one of the plurality of first pixel units electrically connected to the at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel units electrically connected to the at least one of the plurality of second pixel circuits are located in adjacent columns of the array.

2 . The display panel according to claim 1 , wherein;
an orthographic projection of the one of the plurality of first pixel circuits on a plane of the display panel does not overlap an orthographic projection of the one of the plurality of first pixel units on the plane of the display panel; and an orthographic projection of the one of the plurality of second pixel circuits on the plane of the display panel at least partially overlaps an orthographic projection of the one of the plurality of second pixel units on the plane of the display panel; and the display panel further comprises a first connection line configured to connect the one of the plurality of first pixel circuits with the one of the plurality of first pixel units.

3 . The display panel according to claim 2 , wherein;
each of the plurality of first pixel units comprises a first electrode, a light-emitting layer and a second electrode that are stacked, and wherein one of the plurality of first pixel circuits is connected to the first electrode; and the first connection line is provided in a same layer with the first electrode.

4 . The display panel according to claim 2 , wherein;
each of the plurality of first pixel units comprises a first electrode, a light-emitting layer and a second electrode that are stacked, wherein one of the plurality of first pixel circuits is connected to the first electrode; and wherein each of the plurality of first pixel circuits comprises a storage capacitor; and the first display region further comprises a compensation electrode electrically connected to the first electrode of the first pixel unit, and an orthographic projection of the compensation electrode on the plane of the display panel overlaps an orthographic projection of the storage capacitor on the plane of the display panel.

5 . The display panel according to claim 1 , wherein;
at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel circuits are electrically connected to a same first signal line of the plurality of first signal lines, and at least one of the plurality of first pixel units electrically connected to the at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel units electrically connected to the at least one of the plurality of second pixel circuits are located in adjacent rows of the array; and the at least one of the plurality of first pixel circuits and the at least one of the plurality of second pixel circuits which are electrically connected to the same first signal line of the plurality of first signal lines are arranged along the row direction.

6 . The display panel according to claim 5 , further comprising a plurality of power voltage signal lines and a plurality of reference voltage signal lines; and
wherein each of the plurality of first pixel circuits comprises a stabilizing capacitor having a first plate connected to one of the plurality of power voltage signal lines and a second plate connected to one of the plurality of reference voltage signal lines.

7 . The display panel according to claim 5 , wherein;
in the first display region, a number of first pixel units in a row of first pixel units is smaller than a number of first pixel units in a column of first pixel units.

8 . The display panel according to claim 5 , wherein;
in the first display region, a distance between a row of first pixel units and an adjacent row of second pixel units is smaller than a distance between a column of first pixel units and an adjacent column of second pixel units.

9 . The display panel according to claim 1 , wherein:
at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel circuits are electrically connected to a same second signal line of the plurality of second signal lines, at least one of the plurality of first pixel units electrically connected to the at least one of the plurality of first pixel circuits and at least one of the plurality of second pixel units electrically connected to the at least one of the plurality of second pixel circuits are located in adjacent columns; an orthographic projection of the at least one of the plurality of first pixel circuits on a plane of the display panel overlaps an orthographic projection of the at least one of the plurality of first pixel units electrically c

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Ma Yangzhao
• Zhou Ruiyuan
• Chen Yingjie

Classifications

• H10K59/80515

  characterised by their shape · CPC title

• G06F1/1637 Primary

  Details related to the display arrangement, including those related to the mounting of the display in the housing · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H04M1/0266

  for a display module assembly · CPC title

• G06F1/1686

  the I/O peripheral being an integrated camera · CPC title