Display apparatus having a silicon nitride buffer layer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2021288083-A1
Application number	US-202017134585-A
Country	US
Kind code	A1
Filing date	Dec 28, 2020
Priority date	Mar 13, 2020
Publication date	Sep 16, 2021
Grant date	—

Abstract

A display apparatus includes a substrate. A first buffer layer is disposed over the substrate. The first buffer layer includes silicon nitride and has an atomic percentage of hydrogen bonded to silicon of about 0.36 to about 1.01. A thin film transistor is disposed over the first buffer layer. The thin film transistor includes an active layer. A display element is electrically connected to the thin film transistor.

First claim

What is claimed is:

1 . A display apparatus comprising:
a substrate; a first buffer layer disposed on the substrate, the first buffer layer including silicon nitride and having an atomic percentage of hydrogen bonded to silicon of about 0.36 to about 1.01; a thin film transistor disposed over the first buffer layer; and a display element electrically connected to the thin film transistor.

2 . The display apparatus of claim 1 , further comprising a second buffer layer disposed between the first buffer layer and the thin film transistor.

3 . The display apparatus of claim 2 , wherein the second buffer layer includes silicon oxide.

4 . The display apparatus of claim 1 , wherein the thin film transistor comprises a gate electrode and an active layer and the active layer is closer to the first buffer layer than the active layer is to the gate electrode.

5 . The display apparatus of claim 4 , wherein the gate electrode includes aluminum.

6 . The display apparatus of claim 4 , wherein the gate electrode includes a first layer including aluminum, and a second layer disposed on the first layer, the second layer including a material having an etch ratio that is smaller than an etch ratio of aluminum.

7 . The display apparatus of claim 4 , wherein the gate electrode includes a first layer including aluminum, and a second layer disposed on the first layer, the second layer including titanium.

8 . The display apparatus of claim 4 , wherein the gate electrode includes a first layer including aluminum, and a second layer disposed on the first layer, the second layer including titanium nitride.

9 . The display apparatus of claim 8 , wherein the gate electrode further comprises a third layer disposed on the second layer, the third layer including titanium.

10 . A method of manufacturing a display apparatus, the method comprising:
forming a first buffer layer on a substrate, the first buffer layer including silicon nitride and having an atomic percentage of hydrogen bonded to silicon of about 0.36 to about 1.01; forming a thin film transistor over the first buffer layer; and forming a display element electrically connected to the thin film transistor.

11 . The method of claim 10 , further comprising forming a second buffer layer on the first buffer layer,
wherein the forming of the thin film transistor comprises forming the thin film transistor over the second buffer layer.

12 . The method of claim 11 , wherein the forming of the second buffer layer comprises forming a silicon oxide layer.

13 . The method of claim 10 , wherein the forming of the thin film transistor comprises forming an active layer and forming a gate electrode over the active layer.

14 . The method of claim 13 , wherein the gate electrode is formed of a material including aluminum.

15 . The method of claim 13 , wherein the forming of the gate electrode comprises forming a first temporary layer using a material including aluminum, forming a second temporary layer on the first temporary layer using a material having an etch ratio that is less than an etch ratio of aluminum, and simultaneously patterning the first and second temporary layers to form the gate electrode.

16 . The method of claim 13 , wherein the forming of the gate electrode comprises forming a first temporary layer using a material including aluminum, forming a second temporary layer on the first temporary layer using a material including titanium, and simultaneously patterning the first and second temporary layers to form the gate electrode.

17 . The method of claim 13 , wherein the forming of the gate electrode comprises forming a first temporary layer using a material including aluminum, forming a second temporary layer disposed on the first temporary layer using a material including titanium nitride, and simultaneously patterning the first and second temporary layers to form the gate electrode.

18 . The method of claim 13 , wherein the forming of the gate electrode comprises forming a first temporary layer using a material including aluminum, forming a second temporary layer disposed on the first temporary layer using a material including titanium nitride, forming a third temporary layer disposed on the second temporary layer using a material including titanium, and simultaneously patterning the first to third temporary layers to form the gate electrode.

19 . The method of claim 10 , wherein the forming of the first buffer layer comprises forming the first buffer layer using only nitrogen gas and silane gas.

20 . The method of claim 10 , wherein the forming of the first buffer layer comprises forming the first buffer layer by maintaining a flow rate of nitrogen gas to be at least 160 times a flow rate of silane gas.

Assignees

• Samsung Display Co Ltd

Inventors

• Chung Yungbin
• Woo Yeoungkeol
• Kwak Eunjin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/873

  Encapsulations · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title