Gate Structure Passivating Species Drive-In Method and Structure Formed Thereby

Patent metadata

Field	Value
Publication number	US-2021287905-A1
Application number	US-202117334255-A
Country	US
Kind code	A1
Filing date	May 28, 2021
Priority date	Sep 28, 2017
Publication date	Sep 16, 2021
Grant date	—

Abstract

Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

First claim

What is claimed is:

1 . A method comprising:
forming a high-k gate dielectric layer over an active area on a substrate; implanting the high-k gate dielectric layer with fluorine, the implanting the high-k gate dielectric layer comprising, in order:
forming a capping layer;
forming a barrier layer;
forming a dummy fluorine-containing layer, wherein the dummy fluorine-containing layer is formed by an atomic layer deposition process which utilizes a fluorine-containing precursor followed by a second precursor;
forming a capping layer;
performing a thermal process to drive fluorine from the dummy fluorine-containing layer into the high-k gate dielectric layer and from the dummy fluorine-containing layer into the capping layer, wherein the performing the thermal process reduces a concentration of fluorine within the barrier layer; and
removing the dummy fluorine-containing layer; and
forming a metal gate electrode over the high-k gate dielectric layer.

2 . The method of claim 1 , wherein the forming the dummy fluorine-containing layer is performed at a temperature of about 300° C. for a duration of about 97 seconds.

3 . The method of claim 1 , wherein the forming the capping layer is performed at a temperature of about 450° C. for a duration of about 175 seconds.

4 . The method of claim 1 , wherein the performing the thermal process performs a rapid thermal anneal.

5 . The method of claim 4 , wherein the rapid thermal anneal is performed at a temperature of about 575° C. for about 15 seconds.

6 . The method of claim 1 , wherein the removing the dummy fluorine-containing layer is performed using a wet etch process with phosphoric acid (H 3 PO 4 ).

7 . A method comprising:
conformally forming a high-k gate dielectric layer between gate spacers; after the conformally forming the high-k gate dielectric layer, forming a barrier layer over the high-k gate dielectric layer; after the forming the barrier layer, conformally depositing a dummy layer over the barrier layer; after the conformally depositing the dummy layer, forming a dummy capping layer over the dummy layer; after the forming the dummy capping layer, driving fluorine from the dummy layer into the high-k gate dielectric layer and also driving fluorine from the dummy layer into the dummy capping layer, wherein the driving the fluorine from the dummy layer into the high-k gate dielectric layer also reduces a concentration of fluorine in the barrier layer; and after the driving the fluorine from the dummy layer into the high-k gate dielectric layer, removing the dummy layer.

8 . The method of claim 7 , wherein the driving the fluorine from the dummy layer into the high-k gate dielectric layer is performed at least in part with a thermal process.

9 . The method of claim 8 , wherein the thermal process is a rapid thermal anneal.

10 . The method of claim 8 , wherein the thermal process is performed at least in part at a temperature between about 300° C. to about 600° C. for a duration between about 15 seconds to about 180 seconds.

11 . The method of claim 7 , wherein the conformally depositing the dummy layer deposits fluorine-doped tungsten.

12 . The method of claim 11 , wherein the conformally depositing the dummy layer utilizes a tungsten fluoride precursor and a diborane (B 2 H 6 ) precursor.

13 . The method of claim 11 , wherein the conformally depositing the dummy layer utilizes a tungsten fluoride precursor and an ethane (C 2 H 6 ) precursor.

14 . The method of claim 11 , wherein the conformally depositing the dummy layer utilizes a tungsten fluoride precursor and a silane (SiH 4 ) precursor.

15 . A method comprising:
forming a gate dielectric layer over a substrate; depositing a first capping layer over the gate dielectric layer; depositing a dummy fluorine-containing layer with an atomic layer deposition process over the first capping layer, wherein the dummy fluorine-containing layer comprises a first material and fluorine, wherein the fluorine is deposited with the first material, and wherein during the depositing the dummy fluorine-containing layer fluorine diffuses into the gate dielectric layer; depositing a dummy capping layer over the dummy fluorine-containing layer, wherein during the depositing the dummy capping layer fluorine diffuses from the dummy fluorine-containing layer into the gate dielectric layer; performing an anneal, the performing the anneal reducing a concentration of fluorine in a portion of the first capping layer, the performing the anneal further diffusing fluorine from the dummy fluorine-containing layer into the dummy capping layer; removing the dummy fluorine-containing layer; and forming a metal gate electrode over the gate dielectric layer, wherein each of the steps recited herein is performed in the recited order.

16 . The method of claim 15 , wherein the depositing the dummy fluorine-containing layer deposits the dummy fluorine-containing layer to a thickness in a range from about 5 Å to about 50 Å.

17 . The method of claim 15 , wherein the depositing the dummy fluorine-containing layer deposits the dummy fluorine-containing layer with a fluorine concentration of less than about 1 percent.

18 . The method of claim 15 , wherein the depositing the dummy capping layer deposits titanium nitride.

19 . The method of claim 15 , wherein the depositing the dummy capping layer deposits the dummy capping layer to a thickness of between about 5 Å and about 30 Å.

20 . The method of claim 15 , wherein the depositing the dummy fluorine-containing layer deposits fluorine-doped tungsten.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wei Hsiao-Kuan
• Lee Hsien-Ming
• Hsu Chin-You
• Hsu Hsin-Yun
• Yeh Pin-Hsuan

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0132

  the conductor being a metallic silicide · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P50/667

  by liquid etching only · CPC title