Programmable input/output port

Patent metadata

Field	Value
Publication number	US-2021286744-A1
Application number	US-202016820497-A
Country	US
Kind code	A1
Filing date	Mar 16, 2020
Priority date	Mar 16, 2020
Publication date	Sep 16, 2021
Grant date	—

Abstract

A system manages communication between a host device and an end device. The system includes a programmable input/output (I/O) port associated with the host device. The host device is connectable through the programmable I/O port and a cable to a plurality of different types of end devices that are respectively associated with different types of protocols. The system further includes a port manager to detect a signal from an end device interface associated with the end device and determine a type of the end device based on the detected signal. The port manager directs the programmable I/O port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

First claim

1 . A system to manage communication in a computing environment, the system comprising:
a motherboard; a host device mounted upon the motherboard; a plurality of end device interfaces mounted upon and sharing the motherboard, the plurality of end device interfaces being of at least two types; a programmable input/output port associated with the host device, the host device connectable to a plurality of different types of end devices via respective ones of the plurality of end device interfaces and through the programmable input/output port and a cable, the plurality of different types of end devices respectively associated with different types of protocols; and a port manager, the port manager configured to: detect a signal from an end device interface associated with the end device; determine, based on the detected signal, a type of the end device; and direct the programmable input/output port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

2 . The system of claim 1 , wherein the programmable input/output port is to present different signals corresponding to the different protocols respectively associated with the different types of end devices.

3 . The system of claim 1 , wherein the programmable input/output port includes programmable terminals to present the signals.

4 . The system of claim 3 , further comprising a programmable logic device to program the programmable terminals to present the signals.

5 . The system of claim 4 , wherein the port manager is to instruct the programmable logic device to program the programmable terminals to present the signals that correspond to the protocol associated with the determined type of the end device.

6 . The system of claim 1 , wherein the plurality of different types of end devices are respectively associated with different types of end device interfaces including at least one of a non-volatile memory express (“NVME”) backplane, a peripheral component interconnect express (“PCIe”) slot, and an open compute project (“OCP”) slot.

7 . The system of claim 1 , wherein the host device includes a central processing unit (“CPU”).

8 . The system of claim 7 , wherein the end device includes another CPU.

9 . A method to manage communication between a host device and a plurality of end devices, comprising:
detecting a signal from an end device interface associated with the end device, the end device connected to the host device via a cable and a programmable input/output port associated with the host device, the host device connectable to a plurality of different types of end devices via a plurality of end device interfaces, the plurality of different types of end devices respectively associated with different types of protocols; determining, based on the detected signal, a type of the end device; and directing the programmable input/output port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device, wherein:
the host device, the end device interfaces, and the programmable input/output port are supported by a common motherboard.

10 . The method of claim 9 , wherein the programmable input/output port presents different signals corresponding to the different protocols respectively associated with the different types of end devices.

11 . The method of claim 9 , wherein the programmable input/output port includes programmable terminals to present the signals.

12 . The method of claim 11 , wherein directing the programmable input/output port to present signals that correspond to the protocol associated with the determined type of the end device includes instructing a programmable logic device to program the terminals to present the signals.

13 . The method of claim 9 , wherein the plurality of different types of devices are respectively associated with different types of end device interfaces including at least one of a non-volatile memory express (“NVME”) backplane, a peripheral component interconnect express (“PCIe”) slot, and an open compute project (“OCP”) slot.

14 . The method of claim 9 , wherein the host device includes a central processing unit (“CPU”).

15 . (canceled)

16 . A non-transitory computer readable storage medium comprising computer executable instructions stored thereon that, when executed by a processor, cause the processor to manage communication between a host device and an end device by:
detecting a signal from an end device interface associated with the end device, the end device connected to the host device via a cable and a programmable input/output port associated with the host device via respective ones of a plurality of end device interfaces, the host device connectable to a plurality of different types of end devices via a cable and a programmable input/output port associated with the host device, the plurality of different types of end devices respectively associated with different types of protocols, the host device, the plurality of end device interfaces, and the programmable input/output port being operatively coupled with and supported by a common motherboard; determining, based on the detected signal, a type of the end device; and directing the programmable input/output port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

17 . The non-transitory computer readable storage medium of claim 16 , wherein the programmable input/output port is to present different signals corresponding to the different protocols respectively associated with the different types of end devices.

18 . The non-transitory computer readable storage medium of claim 16 , wherein the programmable input/output port includes programmable terminals, and directing the programmable input/output port to present signals that correspond to the protocol associated with the determined type of the end device includes instructing a programmable logic device to program the terminals to present the signals.

19 . The non-transitory computer readable storage medium of claim 16 , wherein plurality of different types of devices are respectively associated with different types of end device interfaces including at least one of a non-volatile memory express (NVME) backplane. peripheral component interconnect express (PCIe) slot, and an open compute project (OCP) slot.

20 . The non-transitory computer readable storage medium of claim 16 , wherein the host device includes a central processing unit (CPU), and the end device includes another CPU.

21 . The system of claim 1 , wherein:
the programmable input/output port is to present the signals; a programmable logic device to program the programmable terminals to present the signals, wherein the port manager is to instruct the programmable logic device to program the programmable terminals to present the signals that correspond to the protocol associated with the determined type of the end device; and wherein the signals are presented by the programmable terminals to a port connector and are represented by a pinout in which the presented signals include a first signal that is presented by the programmable input/output port on a first side of the port connector and a second signal that is presented by the programmable input/output port on a second side of the port conne

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Norton John
• Nien Ku-Hsu
• Nguyen Vincent
• Chen Kuan-Wei

Classifications

• G05B2219/1103

  Special, intelligent I-O processor, also plc can only access via processor · CPC title

• G05B19/054 Primary

  Input/output · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title