Data processing device communicating with memory device and data processing method

Patent metadata

Field	Value
Publication number	US-2021286422-A1
Application number	US-202117335160-A
Country	US
Kind code	A1
Filing date	Jun 1, 2021
Priority date	Sep 21, 2018
Publication date	Sep 16, 2021
Grant date	—

Abstract

A data processing device communicating with a memory device via a memory interface includes: at least one data processor configured to generate first data; a data converter configured to generate second data written to the memory device from the first data; and a controller configured to enable the data converter to generate the second data having a size less than that of the first data to reduce power consumption in at least one of the memory device or the memory interface.

First claim

What is claimed is:

1 . A data processing device configured to process signals transmitted through a communication channel by communicating with a memory device via a memory interface, the data processing device comprising:
at least one data processor configured to generate first data; a data converter configured to generate second data written to the memory device from the first data, the second data having a size that is less than a size of the first data; and a controller configured to enable the data converter such that power consumption of at least one of the memory device or the memory interface, and control the data converter based on channel information that is obtained by processing the signals transmitted through the communication channel.

2 . The data processing device of claim 1 , wherein the controller is further configured to disable the data converter to generate the second data that is the same as the first data, to improve the performance of the data processing device.

3 . The data processing device of claim 1 , further comprising a lookup table that stores information about first electric power consumed by at least one of the memory device or the memory interface by the second data that is the same as the first data,
wherein the controller is configured to control the data converter based on the information about the first electric power.

4 . The data processing device of claim 3 , further comprising a plurality of processors configured to generate the first data,
wherein the information comprises pieces, and each piece respectively corresponds to the plurality of processors, and the controller is configured to control the data converter based on the pieces of the information.

5 . The data processing device of claim 1 , wherein the channel information comprises a block error rate (BLER), and
the controller is configured to enable the data converter when the BLER is lower than a value set in advance.

6 . The data processing device of claim 1 , wherein the channel information comprises a code rate, and
the controller is configured to enable the data converter when the code rate is lower than a value set in advance.

7 . The data processing device of claim 1 , wherein the channel information comprises a modulation and coding scheme (MCS), and
the controller is configured to enable the data converter when an index of the MCS is higher than a value set in advance.

8 . The data processing device of claim 1 , wherein the controller is configured to obtain memory power information corresponding to at least one of the power consumption of the memory device or the memory interface and to control the data converter based on the memory power information.

9 . The data processing device of claim 1 , wherein the data converter is configured to generate the second data by mapping the first data to the second data based on a mapping table.

10 . A data processing device configured to process a signal transmitted through a communication channel, the data processing device comprising:
a data processor configured to generate first data by processing the signal transmitted through the communication channel; a data converter configured to generate second data written to a memory device via the memory interface from the first data, configured to generate the second data having a size less than a size of the first data when being enabled, and configured to generate the second data that is the same as the first data when being disabled; and a controller configured to control the data converter based on channel information that is obtained by processing the signal transmitted through the communication channel.

11 . The data processing device of claim 10 , further comprising a symbol detector configured to extract a symbol from the signal transmitted through the communication channel,
wherein the data processor comprises a retransmission combiner configured to generate a log likelihood ratio (LLR) as the first data from the extracted symbol.

12 . The data processing device of claim 10 , wherein the channel information comprises a block error rate (BLER), and
the controller is configured to enable the data converter when the BLER is lower than a value set in advance.

13 . The data processing device of claim 10 , wherein the channel information comprises a code rate, and
the controller is configured to enable the data converter when the code rate is lower than a value set in advance.

14 . The data processing device of claim 10 , wherein the channel information comprises a modulation and coding scheme (MCS), and
the controller is configured to enable the data converter when an index of the MCS is higher than a value set in advance.

15 . The data processing device of claim 10 , wherein the controller is configured to extract mode information indicating a power mode from the signal transmitted through the communication channel and configured to control the data converter based on the mode information.

16 . The data processing device of claim 15 , wherein the mode information comprises a block error rate (BLER), and
the controller is configured to obtain the BLER and to control the data converter based on the BLER.

17 . The data processing device of claim 15 , wherein the mode information comprises a data decoding level, and
the controller is configured to control the data converter based on the data decoding level.

18 . A method of processing a signal transmitted through a communication channel by communicating with a memory device via a memory interface, the method comprising:
generating first data to be stored in the memory device; converting the first data to second data based on channel information that is obtained by processing the signal transmitted through the communication channel; and writing the second data to the memory device, wherein the converting the first data comprises generating the second data having a size less than a size of the first data to reduce power consumption in at least one of the memory device or the memory interface when the channel information corresponds to a channel status better than a reference set in advance.

19 . The data processing device of claim 18 , wherein the channel information comprises a block error rate (BLER), and
the generating the second data comprises generating the second data when the BLER is lower than a value set in advance.

20 . The data processing device of claim 18 , wherein the channel information comprises a modulation and coding scheme (MCS), and
the generating the second data comprises generating the second data when an index of the MCS is higher than a value set in advance.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Hyun-Gu
• Kim Se-Hyoung

Classifications

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• H03M13/6362

  by puncturing · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title