Display substrate and display device

Patent metadata

Field	Value
Publication number	US-2021280132-A1
Application number	US-202117327937-A
Country	US
Kind code	A1
Filing date	May 24, 2021
Priority date	Sep 30, 2017
Publication date	Sep 9, 2021
Grant date	—

Abstract

A display substrate and a display device. The display substrate includes a pixel circuit in which the driving circuit controls a driving current for driving the light emitter element to emit light; the first light emission control circuit applies a first voltage to a first terminal of the driving circuit in response to a first light emission control signal; the second light emission control circuit applies the driving current to the light emitter element in response to a second light emission control signal; the first reset circuit applies a first reset voltage to the control terminal of the driving circuit in response to a first reset signal; the first reset signal and the first light emission control signal are simultaneously turn-on signals during a period; the first light emission control line and the second light emission control line extend along a first direction and are arranged in a second direction.

First claim

What is claimed is:

1 . A display substrate comprising:
a sub-pixel comprising a pixel circuit, and the pixel circuit comprises: a driving circuit, a data writing circuit, a first reset circuit, a first light emission control circuit, a second light emission control circuit, a light emitter element, a first light emission control line and a second light emission control line, wherein the driving circuit comprises a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light emitter element to emit light; the data writing circuit is configured to write a data signal to the driving circuit in response to a scan signal; the first light emission control circuit is configured to apply a first voltage to the first terminal of the driving circuit in response to a first light emission control signal; the second light emission control circuit is configured to apply the driving current to the light emitter element in response to a second light emission control signal; the first reset circuit is configured to apply a first reset voltage to the control terminal of the driving circuit in response to a first reset signal, and the first reset signal and the first light emission control signal are simultaneously turn-on signals during at least a period of time; the first light emission control line and the second light emission control line respectively substantially extend along a first direction and are arranged in a second direction, and the second direction intersects with the first direction.

2 . The display substrate according to claim 1 , wherein the display substrate comprises a plurality of light emission control lines and a plurality of the sub-pixels distributed in an array; the plurality of light emission control lines comprise the first light emission control line and the second light emission control line; the array comprises a plurality of sub-pixel rows, each sub-pixel row of the plurality of sub-pixel rows comprises the sub-pixels, a first sub-pixel row corresponds to a first one of the plurality of light emission control lines, . . . , an Nth sub-pixel row corresponds to an Nth one of the plurality of light emission control lines, and an (N+1)th sub-pixel row corresponds to an (N+1)th one of the plurality of light emission control lines, and N is an integer greater than 0;
the display substrate comprises: a display region; a non-display region at least partially surrounding the display region; and a peripheral circuit in the non-display region and configured to provide a light emission control signal to the plurality of light emission control lines, wherein the light emission control signal is sequentially provided from the first one of the plurality of light emission control lines to the (N+1)th one of the plurality of light emission control lines.

3 . The display substrate according to claim 2 , wherein
the first light emission control line in the pixel circuit of the Nth sub-pixel row is the (N+1)th one of the plurality of light emission control lines; and the second light emission control line in the pixel circuit of the Nth sub-pixel row is the Nth one of the plurality of light emission control lines.

4 . The display substrate according to claim 2 , wherein
the first light emission control line in the pixel circuit of the Nth sub-pixel row is the Nth one of the plurality of light emission control lines; and the second light emission control line in the pixel circuit of the Nth sub-pixel row is the (N+1)th one of the plurality of light emission control lines.

5 . The display substrate according to claim 1 , wherein the driving circuit comprises a first transistor;
a gate electrode of the first transistor serves as the control terminal of the driving circuit to connect a first node, a first electrode of the first transistor serves as the first terminal of the driving circuit to connect a second node, and a second electrode of the first transistor serves as the second terminal of the driving circuit to connect a third node; the pixel circuit further comprises a storage capacitor which comprises a first electrode plate and a second electrode plate, wherein the first electrode plate is electrically connected with the gate electrode of the first transistor, and the first light emission control line and the second light emission control line are arranged in a same layer as the first electrode plate.

6 . The display substrate according to claim 5 , wherein
the first reset circuit comprises a reset control line extending along the first direction, and the reset control line is connected with a first reset voltage terminal to provide the first reset signal; the first light emission control line, the second light emission control line and the reset control line are sequentially arranged in the second direction and are all at a same side of the storage capacitor in the second direction.

7 . The display substrate according to claim 6 , wherein
the first light emission control line and the second light emission control line are at a side of the reset control line close to the storage capacitor.

8 . The display substrate according to claim 5 , wherein
the display substrate comprises a base substrate, and the sub-pixel is provided on the base substrate; the first transistor comprises an active pattern and a gate electrode, wherein the active pattern of the first transistor comprises a channel region, and an orthographic projection of the channel region of the first transistor on the base substrate overlaps with at least a part of an orthographic projection of the gate electrode of the first transistor on the base substrate; the channel region of the first transistor comprises a first transverse portion, a longitudinal portion and a second transverse portion which are sequentially arranged in the first direction, wherein the first transverse portion and the second transverse portion respectively extend along the first direction and the longitudinal portion extends along the second direction; a first end of the longitudinal portion in the second direction is connected with the first transverse portion, and a second end of the longitudinal portion opposite to the first end of the longitudinal portion in the second direction is connected with the second transverse portion.

9 . The display substrate according to claim 5 , wherein the pixel circuit further comprises:
a semiconductor layer comprising the active pattern of the first transistor; a first connection structure which is in a same layer as the first electrode of the first transistor and has a first end and a second end, wherein the first end of the first connection structure is electrically connected with the first electrode plate through a first via hole, and the second end of the first connection structure is electrically connected with the semiconductor layer; and a second connection structure which is in a same layer as the first electrode of the first transistor and has a first end and a second end, wherein the first end of the second connection structure is electrically connected with the first electrode plate through a second via hole, and the second end of the second connection structure is electrically connected with the semiconductor layer, the first via hole is at a first end of the first electrode plate in the second direction, and the second via hole is at a second end of the first electrode plate opposite to the second end of the first electrode plate in the second direction; the first connection structure is at a first side of the first electrode plate in the second direction, and the second connection struc

Assignees

• Boe Technology Group Co Ltd

Inventors

• Gao Xueling
• Peng Kuanjun
• Yang Chengchung
• Zou Xiangxiang
• Qin Wei

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2320/046

  Dealing with screen burn-in prevention or compensation of the effects thereof · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title