Wrap-Around Contact on FinFET

Patent metadata

Field	Value
Publication number	US-2021272849-A1
Application number	US-202117322007-A
Country	US
Kind code	A1
Filing date	May 17, 2021
Priority date	Apr 21, 2014
Publication date	Sep 2, 2021
Grant date	—

Abstract

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

First claim

What is claimed is:

1 . A field effect transistor (FinFET) device, comprising:
a semiconductor substrate; a first crystalline region over and separated from a semiconductor substrate, the first crystalline region having surfaces oriented in a crystalline plane and being located in a source/drain region of the FinFET device; and an epitaxial layer of semiconductor material formed on the first crystalline region in the source/drain region.

2 . The FinFET device of claim 1 , wherein the semiconductor substrate includes a semiconductor material selected from the group consisting of silicon and silicon germanium.

3 . The FinFET device of claim 1 further comprising a shallow trench isolation (STI) region around the first crystalline region.

4 . The FinFET device of claim 3 , wherein a width of the first crystalline region decreases from a top surface of the STI region towards the semiconductor substrate.

5 . The FinFET device of claim 3 , wherein the first crystalline region directly overlaps at least a portion of the STI region.

6 . The FinFET device of claim 3 , wherein the STI region contacts side surfaces of the first crystalline region.

7 . The FinFET device of claim 1 further comprising a gate structure including a gate conductor.

8 . The FinFET device of claim 7 , wherein the gate conductor comprises titanium nitride, ruthenium, aluminum, or tantalum carbide.

9 . The FinFET device of claim 7 further comprising a high-k dielectric on the gate conductor.

10 . The FinFET device of claim 1 , wherein at least a portion of the epitaxial layer of semiconductor material is wider than first crystalline region.

11 . The FinFET device of claim 1 , wherein the first crystalline region is separated from the semiconductor substrate by a semiconductor-comprising region.

12 . The FinFET device of claim 11 , wherein the semiconductor-comprising region is a second crystalline region.

13 . A field effect transistor (FinFET) device, comprising:
crystalline fin portions separate from a semiconductor substrate layer, the crystalline fin portions being located in source/drain regions of the FinFET device; a dielectric material around the crystalline fin portions, the crystalline fin portions being dielectrically isolated from each other by the dielectric material; and an epitaxial layer of semiconductor material formed on the crystalline fin portions in the source/drain regions.

14 . The FinFET device of claim 13 , wherein the dielectric material touches side surfaces of the crystalline fin portions.

15 . The FinFET device of claim 13 , wherein the dielectric material is a shallow trench isolation (STI) region.

16 . The FinFET device claim 13 , wherein the crystalline fin portions each have tapered sidewalls.

17 . A field effect transistor (FinFET) device, comprising:
a first semiconductor region separate from a semiconductor substrate layer, the first semiconductor region being located in a source/drain region of the FinFET device; and an epitaxial layer of a semiconductor material on the first semiconductor region in the source/drain region, wherein the epitaxial layer is formed directly on surfaces of the first semiconductor region.

18 . The FinFET device of claim 17 , wherein the semiconductor substrate layer includes a material selected from the group consisting of: silicon, germanium, and silicon germanium.

19 . The FinFET device of claim 17 further comprising a shallow trench isolation (STI) region around at least bottom portions of the first semiconductor region.

20 . The FinFET device of claim 19 , wherein a width of first semiconductor region increases in a direction towards a top surface of the STI region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sung-Li
• Chen Neng-Kuo
• Shih Ding-Kang
• Chang Meng-Chun
• Lin Yi-An
• Huang Gin-Chen
• Hsu Chen-Feng
• Lin Hau-Yu
• Ko Chih-Hsin
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title