Wear leveling and access method and device for non-volatile memory, and storage medium

Patent metadata

Field	Value
Publication number	US-2021271398-A1
Application number	US-201917261566-A
Country	US
Kind code	A1
Filing date	Apr 1, 2019
Priority date	Jul 20, 2018
Publication date	Sep 2, 2021
Grant date	—

Abstract

A wear leveling and access method and device for a non-volatile memory, and a storage medium. The method includes: logically dividing a non-volatile memory into physical units of p levels, the non-volatile memory including a plurality of physical units of the first level, each physical unit of the p−1-th level including a plurality of physical units of the p-th level, and p being a positive integer greater than one (S110); when a time period corresponding to the physical units of the q-th level arrives, replacing the data of each of the physical units of the q-th level with other physical units of the q-th level, q being any positive integer from one to p (S120).

First claim

1 . A wear leveling and access method for a non-volatile memory, comprising:
logically dividing the non-volatile memory into p levels of physical units, wherein the non-volatile memory comprises a plurality of 1 st -level physical units, and each (p−1) th -level physical unit comprises a plurality of p th -level physical units, p being a positive integer greater than 1; and migrating, when a time cycle corresponding to q th -level physical units arrives, data in each of the q th -level physical units to another q th -level physical unit, q being any positive integer from 1 to p.

2 . The method according to claim 1 , wherein migrating data in each of the q th -level physical units to another q th -level physical unit comprises:
copying data in each of the q th -level physical units to an external memory or an internal memory, and then copying the data from the external memory or the internal memory to the non-volatile memory to a location where the data of the q th -level physical unit is rotated to.

3 . The method according to claim 1 , wherein migrating data in each of the q th -level physical units to another q th -level physical unit comprises:
copying data in each of the q th -level physical units to a free location in the non-volatile memory or to an external memory or an internal memory, and then copying the data from the free location in the non-volatile memory or from the external memory or the internal memory to the non-volatile memory to a location where the data of the q th -level physical unit is rotated to.

4 . The method according to claim 1 , wherein migrating data in each of the q th -level physical units to another q th -level physical unit comprises:
copying data in a q th -level physical unit to an external memory or an internal memory, copying data in each of other q th -level physical units one by one to a location of last copied data in the non-volatile memory, and then copying the data in the external memory or the internal memory to a location of a last copied data in the non-volatile memory.

5 . The method according to claim 1 , wherein migrating data in each of the q th -level physical units to another q th -level physical unit comprises:
copying data in a q th -level physical unit to a free location in the non-volatile memory or to an external memory or an internal memory, copying data in each of other q th -level physical units one by one to a location of last copied data in the non-volatile memory, and then copying the data at the free location in the non-volatile memory or in the external memory or the internal memory to a location of a last copied data in the non-volatile memory.

6 . The method according to claim 1 , wherein before migrating data in each of the q th -level physical units to another q th -level physical unit, the method further comprises:
setting a time cycle corresponding to the q th -level physical units based on a current working scenario.

7 . The method according to claim 1 , further comprising:
setting, when a user accesses the non-volatile memory, a logical address of an a th physical unit among n q th -level physical units to (x/Q+y/A)% n, wherein x is a logical address of the non-volatile memory, Q is a size of each of the q th -level physical units, y is the user's access time, and A is a time cycle corresponding to the q th -level physical units.

8 . A wear leveling and access device for a non-volatile memory, comprising: a non-volatile memory, a processor, a memory, and a communication bus, wherein:
the communication bus is configured to realize connected communication between the processor and the memory; and the processor is configured to execute a data rotation program stored in the memory so as to implement the following steps: logically dividing the non-volatile memory into p levels of physical units, wherein the non-volatile memory comprises a plurality of 1 st -level physical units, and each (p−1) th -level physical unit comprises a plurality of p th -level physical units, p being a positive integer greater than 1; and migrating, when a time cycle corresponding to q th -level physical units arrives, data in each of the q th -level physical units to another q th -level physical unit, q being any positive integer from 1 to p.

9 . The device according to claim 8 , wherein in migrating data in each of the q th -level physical units to another q th -level physical unit, the processor is configured to execute the data rotation program to implement the following steps:
copying data in each of the q th -level physical units to an external memory or an internal memory, and then copying the data from the external memory or the internal memory to the non-volatile memory to a location where the data of the q th -level physical unit is rotated to.

10 . The device according to claim 8 , wherein in migrating data in each of the q th -level physical units to another q th -level physical unit, the processor is configured to execute the data rotation program to implement the following steps:
copying data in a q th -level physical unit to an external memory or an internal memory, copying data in each of other q th -level physical units one by one to a location of last copied data in the non-volatile memory, and then copying the data in the external memory or the internal memory to a location of a last copied data in the non-volatile memory.

11 . The device according to claim 8 , wherein before migrating data in each of the q th -level physical units to another q th -level physical unit, the processor is further configured to execute the data rotation program to implement the following step:
setting a time cycle corresponding to the q th -level physical units based on a current working scenario.

12 . A wear leveling and access device for a non-volatile memory, comprising: the non-volatile memory and a processor, wherein:
the processor is configured to execute a wear leveling and access program for the non-volatile memory to implement the following steps: logically dividing the non-volatile memory into p levels of physical units, wherein the non-volatile memory comprises a plurality of 1 st -level physical units, and each (p−1) th -level physical unit comprises a plurality of p th -level physical units, p being a positive integer greater than 1; and migrating, when a time cycle corresponding to q th -level physical units arrives, data in each of the q th -level physical units to another q th -level physical unit, q being any positive integer from 1 to p.

13 . The device according to claim 12 , wherein in migrating data in each of the q th -level physical units to another q th -level physical unit, the processor is configured to execute the wear leveling and access program for the non-volatile memory to implement the following steps:
copying data in each of the q th -level physical units to a free location in the non-volatile memory or to an external memory or an internal memory, and then copying the data from the free location in the non-volatile memory or from the external memory or the internal memory to the non-volatile memory to a location where the data of the q th -level physical unit is rotated to.

14 . The device according to claim 12 , wherein in migrating data in each of the q th -level physical units to another q th -level physical unit, the processor is configured to execute the wear leveling and access program for the non-volatile memory to implement the following steps:
copying data in a q th -level physical unit to a free location in the non-volatile memory or to an external memory or an internal memory, copying data in each of other q th -level p

Assignees

• Zte Corp

Inventors

• Yang Hongzhang
• Tu Yaofeng
• Chen Guihai
• Guo Bin
• Han Yinjun
• Yan Zongshuai
• Huang Zhenjiang
• Gao Hong

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G11C16/3495

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title