System and method for uefi advanced graphics utilizing a graphics processing unit

Patent metadata

Field	Value
Publication number	US-2021256652-A1
Application number	US-202016790186-A
Country	US
Kind code	A1
Filing date	Feb 13, 2020
Priority date	Feb 13, 2020
Publication date	Aug 19, 2021
Grant date	—

Abstract

A central processing unit executes a graphics accelerated operation during a pre-boot basic input/output system (BIOS). The central processing unit initializes multiple protocol scheduler circuitry during an early phase of the pre-boot BIOS. The multiple protocol scheduler circuitry initializes host memory pages, and creates one or more bit block transfer tasklets during the pre-boot BIOS. A graphics processing core executes one of the bit block transfer tasklets, and renders a graphical user interface element for display during the pre-boot BIOS.

First claim

What is claimed is:

1 . An information handling system, comprising:
a central processing unit to execute a graphics accelerated operation during a pre-boot basic input/output system (BIOS), the central processing unit to initialize multiple protocol scheduler circuitry during an early phase of the pre-boot BIOS; and a graphics processing unit to communicate with the central processing unit, the graphics processing unit including:
host memory pages;
the multiple protocol scheduler circuitry to initialize the host memory pages, and to create one or more bit block transfer tasklets during the pre-boot BIOS; and
a first graphics processing core to execute one of the bit block transfer tasklets, and to render a graphical user interface element for display during the pre-boot BIOS.

2 . The information handling system of claim 1 , further comprising:
a display device to communicate with the graphics processing unit, the display device to receive the graphical user interface element from the graphics processing unit, and to display the graphical user interface element during the pre-boot BIOS.

3 . The information handling system of claim 1 , wherein the graphics processing unit further includes a plurality of graphics processing cores including the first graphics processing core, each of the graphics processing cores is assigned a different one of the bit block transfer tasklets.

4 . The information handling system of claim 3 , wherein each of the bit block transfer tasklets is an independent task run on the graphics processing unit without central processing unit dependency.

5 . The information handling system of claim 4 , wherein the bit block transfer tasklets are executed in parallel by the graphics processing cores.

6 . The information handling system of claim 1 , wherein in response to execution of the one of the bit block transfer tasklets, the first graphics processing core to move a block of bits from one location in memory to another.

7 . The information handling system of claim 6 , wherein the block of bits represent display pixels, and the movement of the block of bits causes a part of an image to be moved from one place to another on a display.

8 . The information handling system of claim 1 , wherein the graphics accelerated operation, tasks for the multiple protocol scheduler circuitry, and each of the one of the bit block transfer tasklets are individually scheduled in a graphics device interface stack.

9 . The information handling system of claim 1 , wherein the graphical user interface element is selected from a group consisting of icons, widgets, and fonts.

10 . A method, comprising:
executing, by a central processing unit of an information handling system, a graphics accelerated operation during a pre-boot basic input/output system (BIOS); during an early phase of the pre-boot BIOS, initializing, by the central processing unit, multiple protocol scheduler circuitry of a graphics processing unit of the information handling system; initializing, by the multiple protocol scheduler circuitry, host memory pages of the graphics processing unit; creating, by the multiple protocol scheduler circuitry, one or more bit block transfer tasklets during the pre-boot BIOS; executing, by a first graphics processing core of the graphics processing unit, one of the bit block transfer tasklets; and rendering, by the first graphics processing core, a graphical user interface element for display during the pre-boot BIOS.

11 . The method of claim 10 , further comprising:
receiving, by a display device of the information handling system, the graphical user interface element from the graphics processing unit; and displaying, by the display device, the graphical user interface element during the pre-boot BIOS.

12 . The method of claim 10 , further comprising:
assigning a different one of the bit block transfer tasklets to each of a plurality of graphics processing cores including the first graphics processing core.

13 . The method of claim 10 , further comprising:
running each of the bit block transfer tasklets independent on the graphics processing unit without central processing unit dependency.

14 . The method of claim 13 , further comprising:
executing the bit block transfer tasklets in parallel by the graphics processing cores.

15 . The method of claim 10 , wherein in response to the executing of the one of the bit block transfer tasklets, the method further comprises:
moving, by the first graphics processing core, a block of bits from one location in memory to another.

16 . The method of claim 15 , wherein the block of bits represent display pixels, and the movement of the block of bits cause a part of an image to be moved from one place to another on a display.

17 . The method of claim 10 , wherein the graphics accelerated operation, tasks for the multiple protocol scheduler circuitry, and each of the one of the bit block transfer tasklets are individually scheduled in a graphics device interface stack.

18 . An information handling system, comprising:
a central processing unit to execute a graphics accelerated operation during a pre-boot basic input/output system (BIOS), the central processing unit to initialize multiple protocol scheduler circuitry during an early phase of the pre-boot BIOS; a graphics processing unit to communicate with the central processing unit, the graphics processing unit including:
host memory pages;
the multiple protocol scheduler circuitry to initialize the host memory pages, and to create one or more bit block transfer tasklets during the pre-boot BIOS; and
a plurality of graphics processing cores, each of the graphics processing cores being assigned a different one of the bit block transfer tasklets, each of the graphics processing cores to execute one of the bit block transfer tasklets and to render a different graphical user interface element for display during the pre-boot BIOS; and
a display device to receive the graphical user interface element from the graphics processing unit, and to display the graphical user interface element during the pre-boot BIOS.

19 . The information handling system of claim 18 , wherein each of the bit block transfer tasklets is an independent task run on the graphics processing unit without central processing unit dependency.

20 . The information handling system of claim 19 , wherein the bit block transfer tasklets are executed in parallel by the graphics processing cores.

Assignees

• Dell Products Lp

Inventors

• Suryanarayana Shekar Babu
• Joshi Anand

Classifications

• G09G2360/122

  Tiling · CPC title

• G09G5/395

  Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) · CPC title

• G09G2330/026

  Arrangements or methods related to booting a display · CPC title

• G09G5/363

  Graphics controllers · CPC title

• G09G5/37

  Details of the operation on graphic patterns (G09G5/38 takes precedence) · CPC title