Semiconductor devices, semiconductor structures and methods for fabricating a semiconductor structure
US-12176346-B2 · Dec 24, 2024 · US
US2021247239A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2021247239-A1 |
| Application number | US-202016787681-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 11, 2020 |
| Priority date | Feb 11, 2020 |
| Publication date | Aug 12, 2021 |
| Grant date | — |
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A hybrid integrated thermal sensor device includes a magnetic tunnel junction (MTJ) device electrically coupled in series with at least one CMOS transistor and disposed between a voltage rail terminal and a ground terminal. An output terminal is electrically coupled to a drain of the at least one CMOS transistor. The MTJ operates in an anti-parallel state and the output terminal provides a voltage indicative of a temperature of the MTJ device based on an MTJ antiparallel resistance. A distributed sensor network for real-time thermal mapping of an integrated circuit (IC) is also described.
Opening claim text (preview).
What is claimed is: 1 . A hybrid integrated thermal sensor device comprising: a magnetic tunnel junction (MTJ) device electrically coupled in series with at least one CMOS transistor and disposed between a voltage rail terminal and a ground terminal, and an output terminal electrically coupled to a drain of said at least one CMOS transistor; and wherein said MTJ operates in an anti-parallel state and said output terminal provides a voltage indicative of a temperature of said MTJ device based on an MTJ antiparallel resistance. 2 . The hybrid integrated thermal sensor device of claim 1 , comprising said MTJ disposed between a ground terminal and a source terminal of said at least one CMOS transistor, and a second CMOS transistor is disposed between a drain terminal of said at least one CMOS transistor and voltage rail. 3 . The hybrid integrated thermal sensor device of claim 2 , wherein said at least one CMOS transistor comprises a common source amplifier. 4 . The hybrid integrated thermal sensor device of claim 2 , wherein said second CMOS transistor comprises an active load. 5 . The hybrid integrated thermal sensor device of claim 4 , wherein said active load comprises a PMOS based current source. 6 . The hybrid integrated thermal sensor device of claim 1 , further comprising an enable terminal electrically coupled to a gate of at least one CMOS transistor. 7 . The hybrid integrated thermal sensor device of claim 1 , wherein said output terminal is electrically coupled to a first input terminal of a comparator, and a second input of said comparator is electrically coupled to a settable reference voltage. 8 . The hybrid integrated thermal sensor device of claim 7 , wherein said hybrid integrated thermal sensor device operates as a one bit digital thermal sensor with a settable threshold temperature. 9 . The hybrid integrated thermal sensor device of claim 7 , wherein said comparator further comprises a sensor amplifier enable (SAEN) terminal electrically coupled to said comparator. 10 . A distributed sensor network for real-time thermal mapping of an integrated circuit (IC) comprising: a control unit disposed in said IC; a plurality of hybrid MTJ/CMOS integrated thermal sensor devices electrically coupled to said control unit; and wherein said control unit reads of each said hybrid MTJ/CMOS integrated thermal sensor devices to generate substantially in real-time, a thermal map of said IC. 11 . The distributed sensor network of claim 10 , wherein said plurality of hybrid MTJ/CMOS integrated thermal sensor devices comprises more than about 100 devices. 12 . The distributed sensor network of claim 10 , wherein said plurality of hybrid MTJ/CMOS integrated thermal sensor devices comprise one bit digital thermal sensors with a plurality of same or different settable threshold temperatures. 13 . The distributed sensor network of claim 12 , further comprising a multiplexer circuit to switch a reference between different voltages to vary said settable threshold temperature said one bit digital thermal sensors. 14 . The distributed sensor network of claim 10 , wherein said plurality of hybrid MTJ/CMOS integrated thermal sensor devices are configured in a grid based topology of m×n sensor nodes of m columns and n row. 15 . The distributed sensor network of claim 12 , wherein said thermal map comprises nodes below or above a threshold setting of each of said hybrid MTJ/CMOS integrated thermal sensor devices. 16 . The distributed sensor network of claim 12 , wherein each of said plurality of hybrid MTJ/CMOS integrated thermal sensor devices is sequentially enabled and read by said control unit. 17 . The distributed sensor network of claim 12 , wherein said control unit or a different control unit of said IC dynamically manages at least one system of said IC based on said thermal map to mitigate deterioration of a lifetime of said IC or a reliability of said IC. 18 . The distributed sensor network of claim 10 , wherein said control unit, or a different control unit, dynamically configures substantially in real-time at least one logic module or at least one memory module of said IC based on said thermal map of said IC. 19 . The distributed sensor network of claim 18 , wherein based on said thermal map, said control unit, or said different control unit dynamically moves execution of a logic or an execution of a memory function from one module to a different similar function module of said IC dynamically in time to balance a thermal load between modules or to prevent an overheating of a module. 20 . The distributed sensor network of claim 18 , wherein based on said thermal map, said control unit, or said different control unit, dynamically reconfigures said IC to optimize a thermal condition of said IC.
Circuits arrangements for indicating a predetermined temperature (fire detection G08B17/00) · CPC title
Temperature mapping · CPC title
using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title
arrangements for monitoring a plurality of temperatures, e.g. by multiplexing · CPC title
using resistive elements · CPC title
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