Switching converter with pulse truncation control

Patent metadata

Field	Value
Publication number	US-2021242779-A1
Application number	US-202117238979-A
Country	US
Kind code	A1
Filing date	Apr 23, 2021
Priority date	Sep 27, 2019
Publication date	Aug 5, 2021
Grant date	—

Abstract

A system includes a load and a switching converter coupled to the load. The switching converter includes at least one switching module and an output inductor coupled to a switch node of each switching module. The switching converter also includes a controller coupled to each switching module, where the controller is configured to adjust a pulse clock rate and a switch on-time for each switching module. The controller comprises a pulse truncation circuit configured to detect a voltage overshoot condition and to truncate an active switch on-time pulse in response to the detected voltage overshoot condition.

First claim

What is claimed is:

1 . A circuit comprising:
a first comparator having a first comparator input, a second comparator input, and a first comparator output, the first comparator input adapted to be coupled to a switching output; a compensation circuit comprising a second comparator and a latch, the second comparator having a third comparator input, a fourth comparator input, and a second comparator output; a logic circuit having a first logic input, a second logic input, and a logic output, the first logic input coupled to the first comparator output and the second logic input coupled to the second comparator output; and the latch having a latch input coupled to the logic output.

2 . The circuit of claim 1 , wherein the compensation circuit configured to extend at least one later pulse in response to a truncated pulse.

3 . The circuit of claim 1 , wherein the compensation circuit is configured to determine an amount of pulse truncation and to extend only one single-phase pulse based on the amount of pulse truncation.

4 . The circuit of claim 1 , wherein the compensation circuit is configured to determine an amount of pulse truncation and to extend multiple single-phase pulses based on the amount of pulse truncation.

5 . The circuit of claim 1 , wherein the compensation circuit is configured to determine when pulse truncation is performed and to adjust at least one later pulse for one or more of the switching circuits in response to the pulse truncation.

6 . The circuit of claim 5 , wherein the compensation circuit is configured to determine an amount of pulse truncation associated with a given switching circuit and to adjust at least one later pulse for one or more of the switching circuits based on the amount of pulse truncation.

7 . The circuit of claim 6 , wherein the compensation circuit is configured to extend a plurality of multi-phase pulses based on the amount of pulse truncation.

8 . The circuit of claim 6 , wherein the compensation circuit is configured to reduce a plurality of multi-phase pulses based on the amount of pulse truncation.

9 . A method, comprising:
in response to detecting a voltage overshoot condition, truncating, by pulse truncation circuitry, a first pulse; and in response to detecting that the pulse truncation circuit truncates the first pulse, adjusting, by compensation circuitry, a duration of a second pulse.

10 . The method of claim 9 , further comprising extending, by the compensation circuitry, the second pulse in response to the pulse truncation.

11 . The method of claim 9 , further comprising:
determining, by the compensation circuitry, an amount of pulse truncation; and extending only one pulse based on the amount of pulse truncation.

12 . The method of claim 9 , further comprising:
determining, by the compensation circuitry, an amount of pulse truncation; and extending multi-phase pulses based on the amount of pulse truncation.

13 . The method of claim 9 , further comprising:
determining, by the compensation circuitry, an amount of pulse truncation; and reducing multi-phase pulses based on the amount of pulse truncation.

14 . A system, comprising:
a first switching circuit; a second switching circuit; and a controller coupled to the first switching circuit and to the second switching circuit, the controller comprising:
a loop compensation circuit;
a phase manager coupled to the loop compensation circuit;
a first on-time generation circuit coupled to the first switching circuit and to the phase manager;
a second on-time generation circuit coupled to the second switching circuit and to the phase manager.

15 . The system of claim 14 , wherein the loop compensation circuit is configured to produce a clock signal, a combined current value, and an average inductor current value.

16 . The system of claim 15 , wherein the phase manager circuit is configured to:
select a first phase for the first on-time generation circuit.

17 . The system of claim 14 , wherein the switching circuit is adapted to be coupled to a load, and the load comprises a multi-core processor.

18 . The system of claim 14 , further comprising:
a first inductor coupled to the first switching circuit; and a second inductor coupled to the second switching circuit.

19 . The system of claim 18 , wherein the controller further comprises a current sharing circuit coupled to the first on-time generation circuit and to the second on-time generation circuit.

20 . The system of claim 19 , wherein the first switching circuit comprises:
a gate driver; power transistors coupled to the gate driver; and a current sensing circuit coupled to the power transistors and to the current sharing circuit.

Assignees

• Texas Instruments Inc

Inventors

• Cheng Kuang-Yao
• Venkateswaran Muthusubramanian
• Suryanarayana Dattatreya Baragur
• Tadeparthy Preetam Charan Anand

Classifications

• H02M1/0067

  Converter structures employing plural converter units, other than for parallel operation of the units on a single load · CPC title

• H02M3/1566

  with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title