Method of Packaging an Integrated Circuit

Patent metadata

Field	Value
Publication number	US-2021242097-A1
Application number	US-201917264057-A
Country	US
Kind code	A1
Filing date	Jul 31, 2019
Priority date	Aug 2, 2018
Publication date	Aug 5, 2021
Grant date	—

Abstract

A method of packaging an integrated circuit includes (a) providing: (i) an integrated circuit (e.g., in wafer form) having a two-dimensional contact array on a top surface thereof, (ii) a polymer shell lower portion, and (iii) a polymer shell upper portion, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two dimensional contact array; wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing; and (b) enclosing said integrated circuit between said polymer shell lower portion and said polymer shell upper portion with said contact array aligned with array of openings to produce a integrated circuit packaged within a polymer shell.

First claim

1 . A method of packaging an integrated circuit, comprising the steps of:
(a) providing: (i) an integrated circuit having a two-dimensional contact array on a top surface thereof, (ii) a polymer shell lower portion, and (iii) a polymer shell upper portion, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two dimensional contact array; wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing; and (b) enclosing said integrated circuit between said polymer shell lower portion and said polymer shell upper portion with said contact array aligned with array of openings to produce a integrated circuit packaged within a polymer shell.

2 . The method of claim 1 , further comprising:
(c) filling said openings with a conductor to produce an external contact array on the surface of said polymer shell corresponding to and in electrical contact with said two-dimensional contact array.

3 . The method of claim 1 , wherein said integrated circuit is provided without a lead frame, and is enclosed in said polymer shell without a lead frame.

4 . The method of claim 1 , wherein one or both of said polymer shell upper and lower portions includes at least one heat dissipation feature.

5 . The method of claim 1 , wherein said polymer shell upper and lower portions both include cooperating interlocking alignment features thereon.

6 . The method of claim 1 , wherein said process of additive manufacturing comprises a bottom-up or top-down stereolithography process (e.g., continuous liquid interface production, or “CLIP”).

7 . The method of claim 1 , wherein one or both of said polymer shell upper and lower portions are produced from a dual cure resin.

8 . The method of claim 1 , wherein said packaged integrated circuit is baked to further cure said polymer shell.

9 . The method of claim 1 , wherein said encapsulated object comprises multiple interconnected devices.

10 . A product produced by a process comprising:
(a) providing: (i) an integrated circuit having a two-dimensional contact array on a top surface thereof, (ii) a polymer shell lower portion, and (iii) a polymer shell upper portion, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two dimensional contact array, wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing, and (b) enclosing said integrated circuit between said polymer shell lower portion and said polymer shell upper portion with said contact array aligned with array of openings to produce a integrated circuit packaged within a polymer shell.

11 . A packaged integrated circuit product, comprising:
(a) an integrated circuit having a two-dimensional contact array on a top surface thereof, (b) a polymer shell lower portion, and (c) a polymer shell upper portion connected to said polymer shell lower portion with said integrated circuit enclosed therein, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two-dimensional contact array; wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing; and (d) optionally but preferably a conductor filing said openings and providing an external contact array on the surface of said polymer shell corresponding to and electrically connected to said two-dimensional contact array.

12 . The product of claim 11 , wherein said integrated circuit is enclosed in said polymer shell without a lead frame.

13 . The product of claim 11 , wherein one or both of said polymer shell upper and lower portions includes at least one heat dissipation feature.

14 . The product of claim 11 , wherein said polymer shell upper and lower portions both include cooperating interlocking alignment features thereon.

15 . The method of claim 11 , wherein said process of additive manufacturing comprises a bottom-up or top-down stereolithography process.

16 . The product of claim 11 , wherein one or both of said polymer shell upper and lower portions are produced from a dual cure resin.

17 . The product of claim 11 , wherein said encapsulated integrated circuit comprises multiple interconnected devices.

18 . The method of claim 7 , wherein said dual cure resin comprises an epoxy dual cure resin in a green state that is photopolymerized, but not further cured.

19 . The method of claim 9 , wherein said multiple interconnected devices comprise two integrated circuits directly connected to one another, said two integrated circuits comprising wafer-level dies packaged together; multiple stacks of dies packaged together; wafer-level dies packaged with other MEMS or optoelectronics; finished dies with MEMS or optoelectronics packaged together; GPU/CPU chips with memory die packaged together (optionally combined with cooling channels etc. in the polymer shell); or multiple NAND die with controller packaged together (optionally combined with cooling channels etc. in the polymer shell)).

20 . The product of claim 11 , wherein said multiple interconnected devices comprise two integrated circuits directly connected to one another, said two integrated circuits comprising wafer-level dies packaged together; multiple stacks of dies packaged together; wafer-level dies packaged with other MEMS or optoelectronics; finished dies with MEMS or optoelectronics packaged together; GPU/CPU chips with memory die packaged together (optionally combined with cooling channels etc. in the polymer shell); or multiple NAND die with controller packaged together (optionally combined with cooling channels etc. in the polymer shell)).

Assignees

• Carbon Inc

Inventors

• Holton William C
• Troise James Patrick
• Chadha Gurjeev
• Desimone Joseph M

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/01208

  using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks · CPC title