Detection circuit of gate driver, array substrate, display device and detection method thereof

Patent metadata

Field	Value
Publication number	US-2021241663-A1
Application number	US-201916758900-A
Country	US
Kind code	A1
Filing date	Sep 27, 2019
Priority date	Oct 31, 2018
Publication date	Aug 5, 2021
Grant date	—

Abstract

The present disclosure discloses a detection circuit of a gate driver, an array substrate, a display device and a detection method thereof. Gate scanning signals of each of the signal output ends are derived to a detection signal line through signal deriving circuits, such that the gate scanning signals are transmitted to a discrimination circuit outside the array substrate. The discrimination circuit can acquire in real time and record the gate scanning signals, so as to detect the gate scanning signals in real time, and further rapidly diagnose whether the gate scanning signals are abnormal based on detection results, and rapidly locate the positions at which the gate scanning signals are abnormal, so as to timely troubleshoot the fault.

First claim

1 . A detection circuit of a gate driver, comprising:
a plurality of first signal deriving sub-circuits, wherein a control end of each first signal deriving sub-circuit is coupled with a control signal line, and an input end of the each first signal deriving sub-circuit is coupled with at least one signal output end of the gate driver; and a plurality of second signal deriving sub-circuits, wherein the plurality of second signal deriving sub-circuits are in one-to-one correspondence with the plurality of first signal deriving sub-circuits, a control end of each second signal deriving sub-circuit is coupled with an output end of a corresponding first signal deriving sub-circuit, the control end of the each second signal deriving sub-circuit is coupled with a signal output end which is coupled with the corresponding first signal deriving sub-circuit, and an output end of the each second signal deriving sub-circuit is coupled with a detection signal line.

2 . The detection circuit of a gate driver of claim 1 , wherein the plurality of second signal deriving sub-circuits are coupled with the same detection signal line; and
timing sequences of gate scanning signals output by each of the at least one signal output end corresponding to the each second signal deriving sub-circuit which is coupled with the same detection signal line are not overlapped with each other.

3 . The detection circuit of a gate driver of claim 1 , wherein the gate driver comprises a plurality of cascaded shifting registers, each shifting register comprises at least two signal output ends, and respective signal output ends of the each shifting register are coupled with different detection signal lines.

4 . The detection circuit of a gate driver of claim 1 , wherein the each first signal deriving sub-circuit comprises a first switch transistor, a gate of the first switch transistor is coupled with the control signal line, a first electrode of the first switch transistor is coupled with a corresponding signal output end, and the second electrode of the first switch transistor is coupled with a corresponding second signal deriving sub-circuit.

5 . The detection circuit of a gate driver of claim 1 , wherein the each second signal deriving sub-circuit comprises a second switch transistor, a gate of the second switch transistor is coupled with a corresponding signal output end, a first electrode of the second switch transistor is coupled with the corresponding first signal deriving sub-circuit, and the second electrode of the second switch transistor is coupled with a corresponding detection signal line.

6 . The detection circuit of a gate driver of claim 1 , wherein respective first signal deriving sub-circuits are coupled with the same control signal line.

7 . The detection circuit of a gate driver of claim 1 , further comprising a discrimination circuit, and the discrimination circuit comprises:
an analogue-to-digital conversion circuit configured to be coupled with the detection signal line; and a counting circuit configured to be coupled with the analogue-to-digital conversion circuit.

8 . The detection circuit of a gate driver of claim 6 , further comprising:
a first control circuit, wherein a control end of the first control circuit is coupled with a first clock signal end, an input end of the first control circuit is coupled with a first reference signal end, and an output end of the first control circuit is coupled with one end of the control signal line; and a second control circuit, wherein a control end of the second control circuit is coupled with a second clock signal end, an input end of the second control circuit is coupled with a second reference signal end, and an output end of the second control circuit is coupled with the other end of the control signal line.

9 . The detection circuit of a gate driver of claim 8 , wherein the first control circuit comprises a third switch transistor, wherein a gate of the third switch transistor is coupled with the first clock signal end, a first electrode of the third switch transistor is coupled with the first reference signal end, and a second electrode of the third switch transistor is coupled with the control signal line.

10 . The detection circuit of a gate driver of claim 8 , wherein the second control circuit comprises a fourth switch transistor, wherein a gate of the fourth switch transistor is coupled with the second clock signal end, a first electrode of the fourth switch transistor is coupled with the second reference signal end, and a second electrode of the fourth switch transistor is coupled with the control signal line.

11 . The detection circuit of a gate driver of claim 1 , wherein the each first signal deriving sub-circuit comprises a first switch transistor, the each second signal deriving sub-circuit comprises a second switch transistor, wherein a gate of the first switch transistor is coupled with the control signal line, a first electrode of the first switch transistor and a gate of the second switch transistor are coupled with the same signal output end, a second electrode of the first switch transistor is coupled with a first electrode of the second switch transistor, and a second electrode of the second switch transistor is coupled with the corresponding detection signal line;
the detection circuit further comprises a third switch transistor and a fourth switch transistor, wherein a gate of the third switch transistor is coupled with the first clock signal end, a first electrode of the third switch transistor is coupled with the first reference signal end, a second electrode of the third switch transistor is coupled with one end of the control signal line, a gate of the fourth switch transistor is coupled with the second clock signal end, a first electrode of the fourth switch transistor is coupled with a second reference signal end, and a second electrode of the fourth switch transistor is coupled with the other end of the control signal line.

12 . An array substrate, comprising:
a gate driver, comprising a plurality of signal output ends; a plurality of gate lines, wherein one of the plurality of gate lines is coupled with one of the plurality of signal output ends; a plurality of drive circuits arranged in an array, wherein one of the plurality of drive circuits is coupled with at least one gate line; and the detection circuit of claim 1 .

13 . The array substrate of claim 12 , wherein the gate driver comprises a plurality of cascaded shifting registers, wherein each shifting register comprises two signal output ends which are respectively a first signal output end and a second signal output end;
each drive circuit comprises: a fifth switch transistor, wherein a gate of the fifth switch transistor is coupled with the first signal output end through one gate line, and a source of the fifth switch transistor is coupled with a data line; a drive transistor, wherein a gate of the drive transistor is coupled with a drain of the fifth switch transistor, and a source of the drive transistor is coupled with a first supply voltage signal end; a sixth switch transistor, wherein a gate of the sixth switch transistor is coupled with the second signal output end through one gate line, a source of the sixth switch transistor is coupled with a drain of the drive transistor, and a drain of the sixth switch transistor is coupled with an induction signal line; a capacitor, coupled between the gate of the drive transistor and the drain of the drive transistor; and a to-be-driven element, coupled between the drain of the drive transistor and a second supply voltage signal end.

14 . The array

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Li Meng
• Song Zhigang

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title