Semiconductor device

Patent metadata

Field	Value
Publication number	US-2021233842-A1
Application number	US-202117231915-A
Country	US
Kind code	A1
Filing date	Apr 15, 2021
Priority date	Jan 8, 2019
Publication date	Jul 29, 2021
Grant date	—

Abstract

A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate having a first region, a second region, and a buffer region between the first region and the second region; a lower interlayer dielectric layer on the substrate; a conductive line on a top surface of the lower interlayer dielectric layer on the first region of the substrate; a dummy pattern on the top surface of the lower interlayer dielectric layer on the buffer region of the substrate; and an inductor on the second region of the substrate, wherein: the inductor includes a conductor on the top surface of the lower interlayer dielectric layer, and a top surface of the conductive line is provided at a different level from that of a top surface of the conductor, when viewed in plan, a minimum distance between the dummy pattern and the conductive lines is less than a minimum distance between the dummy pattern and the inductor.

2 . The semiconductor device of claim 1 , wherein a level difference between a top surface of the dummy pattern and the top surface of the conductive line is less than a level difference between the top surface of the conductor and the top surface of the dummy pattern.

3 . The semiconductor device of claim 1 , wherein:
the buffer region includes:
a first buffer region between the first region and the second region; and
a second buffer region between the first buffer region and the second region, and
the dummy pattern is provided on the first buffer region of the substrate and is not provided on the second buffer region of the substrate.

4 . The semiconductor device of claim 1 , wherein the top surface of the lower interlayer dielectric layer on the first region of the substrate is provided at a different level from that of the top surface of the lower interlayer dielectric layer on the second region of the substrate.

5 . The semiconductor device of claim 1 , further comprising:
an upper interlayer dielectric layer on the lower interlayer dielectric layer, wherein: the upper interlayer dielectric layer includes:
a first top surface on the first region of the substrate; and
a second top surface on the second region of the substrate and connected to the first top surface, and
the first top surface is provided at a different level from that of the second top surface.

6 . The semiconductor device of claim 5 , wherein
the top surface of the conductive line is coplanar with the first top surface of the upper interlayer dielectric layer, and the top surface of the conductor is coplanar with the second top surface of the upper interlayer dielectric layer.

7 . The semiconductor device of claim 1 , further comprising:
a lower conductive line on the lower interlayer dielectric layer on the first region of the substrate; and a lower dummy pattern in the lower interlayer dielectric layer on the buffer region of the substrate, wherein the inductor is not provided in the lower interlayer dielectric layer.

8 . The semiconductor device of claim 7 , wherein the dummy pattern is not provided on and in the lower interlayer dielectric layer on the second region of the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Joon-Nyung
• Ahn Jeong Hoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H01L23/528

  Electricity · mapped topic