Erasing memory

Patent metadata

Field	Value
Publication number	US-2021233591-A1
Application number	US-202117228807-A
Country	US
Kind code	A1
Filing date	Apr 13, 2021
Priority date	Aug 29, 2019
Publication date	Jul 29, 2021
Grant date	—

Abstract

Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

First claim

What is claimed is:

1 . A method of operating a memory, comprising:
applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells; and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

2 . The method of claim 1 , further comprising:
while the voltage level applied to the first node is at the third voltage level, applying a voltage level to a control gate of a memory cell of the string of series-connected memory cells expected to remove charge from a data storage structure of the memory cell.

3 . The method of claim 2 , further comprising applying the voltage level to the control gate of the memory cell before increasing the voltage level applied to the first node to the third voltage level.

4 . The method of claim 1 , wherein a voltage difference between the first voltage level and the second voltage level is equal to a voltage difference between the third voltage level and the fourth voltage level.

5 . The method of claim 4 , wherein the voltage difference between the first voltage level and the second voltage level is equal to a voltage difference sufficient to generate gate-induced drain leakage (GIDL) current through the transistor.

6 . The method of claim 4 , wherein increasing the voltage level applied to the first node to the third voltage level has a particular duration, and wherein increasing the voltage level applied to the control gate of the transistor to the fourth voltage level has the particular duration.

7 . The method of claim 1 , wherein increasing the voltage level applied to the first node and increasing the voltage level applied to the control gate of the transistor comprises increasing the voltage level applied to the first node at a particular rate and increasing the voltage level applied to the control gate of the transistor at the particular rate.

8 . The method of claim 7 , wherein increasing the voltage level applied to the first node at the particular rate and increasing the voltage level applied to the control gate of the transistor at the particular rate further comprises increasing the voltage level applied to the first node and increasing the voltage level applied to the control gate of the transistor at a variable rate.

9 . The method of claim 1 , wherein increasing the voltage level applied to the first node to the third voltage level comprises increasing the voltage level applied to the first node to the third voltage level using a first plurality of step changes in voltage level, and wherein increasing the voltage level applied to the control gate of the transistor to the fourth voltage level comprises increasing the voltage level applied to the control gate of the transistor to the fourth voltage level using a second plurality of step changes in voltage level.

10 . The method of claim 1 , further comprising:
applying a positive fifth voltage level to a second node selectively connected to the string of series-connected memory cells while applying a negative sixth voltage level to a control gate of a transistor connected between the second node and the string of series-connected memory cells; and increasing the voltage level applied to the second node to a seventh voltage level while increasing the voltage level applied to the control gate of the transistor connected to the second node to an eighth voltage level lower than the seventh voltage level and higher than the fifth voltage level.

11 . The method of claim 10 , wherein the fifth voltage level equals the first voltage level, the sixth voltage level equals the second voltage level, the seventh voltage level equals the third voltage level, and the eighth voltage level equals the fourth voltage level.

12 . A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to perform a method comprising:
applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells of the plurality of strings of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells; and
increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

13 . A method of operating a memory, comprising:
applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells; increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate; and when the voltage level applied to the first node reaches a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

14 . The method of claim 13 , further comprising:
while the voltage level applied to the first node is at the particular voltage level, applying a voltage level to a control gate of a memory cell of the string of series-connected memory cells expected to remove charge from a data storage structure of the memory cell.

15 . The method of claim 14 , further comprising applying the voltage level to the control gate of the memory cell before the voltage level applied to the first node, and increased at the particular rate, reaches the particular voltage level.

16 . The method of claim 13 , wherein applying the negative first voltage level to the control gate of the transistor connected between the first node and the string of series-connected memory cells comprises applying the negative first voltage level to a control gate of a transistor connected between the string of series-connected memory cells and a particular node selected from a group consisting of a source selectively connected to the string of series-connected memory cells and a data line selectively connected to the string of series-connected memory cells.

17 . The method of claim 13 , wherein applying the negative first voltage level to the control gate of the transistor comprises decreasing the voltage level applied to the control gate of the transistor from an initial voltage level to the first voltage level, and wherein the method further comprises:
increasing a voltage level applied to the first node from the initial voltage level to a second voltage level while decreasing the voltage level applied to the control gate of the transistor from the initial voltage level to the first voltage level.

18 . The method of claim 13 , wherein applying the negative first voltage level to the control gate of the transistor comprises decreasing the voltage level applied to the control gate of the transistor from an initial voltage level to the first voltage level, and wherein the meth

Assignees

• Micron Technology Inc

Inventors

• Paolucci Giovanni Maria
• Tessariol Paolo
• Camerlenghi Emilio
• Carnevale Gianpietro
• Benvenuti Augusto

Classifications

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/30

  Power supply circuits · CPC title