Memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-2021217456-A1
Application number	US-202016922385-A
Country	US
Kind code	A1
Filing date	Jul 7, 2020
Priority date	Jan 15, 2020
Publication date	Jul 15, 2021
Grant date	—

Abstract

A memory device, and a method of operating the memory device, includes: a memory cell array including a plurality of strings; a voltage generation circuit configured to apply a turn-on voltage to the plurality of strings during a set application period in a channel initialization operation of a read operation of a selected string among the plurality of strings; a temperature detection circuit configured to measure an internal temperature of the memory device and generate a temperature signal; and control logic configured to control the voltage generation circuit to set the application period in response to the temperature signal and apply the turn-on voltage to the plurality of strings during the set application period.

First claim

What is claimed is:

1 . A memory device comprising:
a memory cell array including a plurality of strings; a voltage generation circuit configured to apply a turn-on voltage to the plurality of strings during a set application period in a channel initialization operation of a read operation of a selected string among the plurality of strings; a temperature detection circuit configured to measure an internal temperature of the memory device and generate a temperature signal; and control logic configured to control the voltage generation circuit to set the application period in response to the temperature signal and apply the turn-on voltage to the plurality of strings during the set application period.

2 . The memory device according to claim 1 , wherein, based on the temperature signal, the control logic is configured to set the application period to a relatively short period when the internal temperature of the memory device is relatively high, and sets the application period to a relatively long period when the internal temperature of the memory device is relatively low.

3 . The memory device according to claim 1 , wherein the plurality of strings share one source select line per at least two strings, and the at least two strings are relatively coupled to different drain select lines.

4 . The memory device according to claim 3 , wherein the at least two strings are coupled in parallel between a bit line and a source line.

5 . The memory device according to claim 3 ,
wherein each of the plurality of memory strings includes a drain select transistor, a plurality of memory cells, and the source select transistor that are coupled in series between a bit line and a source line, and wherein the voltage generation circuit is configured to generate the turn-on voltage and applies the generated turn-on voltage to the drain select transistor and the source select transistor of an unselected string of the at least two strings during the set application period.

6 . The memory device according to claim 5 , wherein the voltage generation circuit is configured to apply the generated turn-on voltage to the drain select transistor and the source select transistor of the selected string of the at least two strings during a fixed application period.

7 . The memory device according to claim 1 , wherein the control logic is configured to control the voltage generation circuit to perform a read voltage application operation of applying a read voltage and a pass voltage to word lines of the selected string after the channel initialization operation.

8 . The memory device according to claim 7 , wherein the control logic is configured to control the voltage generation circuit to apply the pass voltage to the word lines during the channel initialization operation.

9 . The memory device according to claim 1 , wherein the voltage generation circuit comprises:
a voltage generator configured to generate the turn-on voltage in response to control of the control logic; and an address decoder configured to apply the turn-on voltage to the plurality of strings in response to control of the control logic during the set application period.

10 . A memory device comprising:
a memory cell array including a plurality of strings; a temperature detection circuit configured to detect an internal temperature of the memory device and generate a temperature signal; a voltage generation circuit configured to apply a turn-on voltage to select lines of a selected string and an unselected string of the plurality of strings during a channel initialization operation of a read operation; and control logic configured to control, during the channel initialization operation, the voltage generation circuit to apply the turn-on voltage to the select lines of the selected string during a fixed application time, and apply the turn-on voltage to the select lines of the unselected strings during a variable time, wherein the control logic is configured to vary an application time of the turn-on voltage to be applied to the unselected strings in response to the temperature signal.

11 . The memory device according to claim 10 , wherein, based on the temperature signal, the control logic is configured to set the application time to a relatively short time when the internal temperature of the memory device is relatively high, and sets the application time to a relatively long time when the internal temperature of the memory device is relatively low.

12 . The memory device according to claim 10 , wherein the plurality of strings share one source select line per at least two strings, and the at least two strings are relatively coupled to different drain select lines.

13 . The storage device according to claim 12 , wherein the at least two strings are coupled in parallel between a bit line and a source line.

14 . The memory device according to claim 10 , wherein the control logic is configured to control the voltage generation circuit to perform a read voltage application operation of applying a read voltage and a pass voltage to word lines of the selected string after the channel initialization operation.

15 . The memory device according to claim 14 , wherein the control logic is configured to control the voltage generation circuit to apply the pass voltage to the word lines during the channel initialization operation.

16 . A method of operating a memory device, comprising:
measuring an internal temperature of the memory device; setting a turn-on voltage application period of a channel initialization operation based on the measured internal temperature; applying a turn-on voltage to select transistors of an unselected string among a plurality of strings during the set turn-on voltage application period; and applying a pass voltage to word lines of the plurality of strings.

17 . The method according to claim 16 , wherein setting the turn-on voltage application period of the channel initialization operation based on the measured internal temperature comprises:
reducing, as the measured temperature is increased, the set application period of the turn-on voltage application period; and increasing, as the measured temperature is reduced, the set application period of the turn-on voltage application period.

18 . The method according to claim 16 , wherein applying the turn-on voltage to the select transistors of the unselected string comprises applying the turn-on voltage to the select transistors of a selected string among the plurality of strings, wherein the turn-on voltage application period of the selected string is fixed regardless of the internal temperature.

19 . The method according to claim 18 , wherein the plurality of strings share word lines.

20 . The method according to claim 19 , wherein applying the turn-on voltage to the select transistors of the unselected string comprises applying a pass voltage to the word lines.

Assignees

• Sk Hynix Inc

Inventors

• Choi Gil Bok
• Seo Moon Sik

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/32

  Timing circuits · CPC title