Systems and methods for hardware root of trust with protected redundant memory for authentication failure scenarios

US2021216640A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021216640-A1
Application numberUS-202016740277-A
CountryUS
Kind codeA1
Filing dateJan 10, 2020
Priority dateJan 10, 2020
Publication dateJul 15, 2021
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A cryptoprocessor may comprise processing logic configured to upon powering up of a management controller communicatively coupled to a processor of an information handling system and configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling system, preventing the management controller from booting, attempt to authenticate a primary executable code image stored in a primary memory and a backup image to the primary executable code image stored in a secondary memory, and responsive to at least one of the primary executable code image and the backup image being authenticated, allow the management controller to execute an authenticated image comprising one of the primary executable code image and the backup image.

First claim

Opening claim text (preview).

What is claimed is: 1 . An information handling system comprising: a processor; a management controller communicatively coupled to the processor and configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling system; a primary memory for storing a primary executable code image associated with the management controller; a secondary memory for storing a backup image to the primary executable code image; and a cryptoprocessor communicatively coupled to the management controller and configured to: upon powering up of the management controller, preventing the management controller from booting from either of the primary executable code image and the backup image; attempt to authenticate the primary executable code image and the backup image; and responsive to at least one of the primary executable code image and the backup image being authenticated, allow the management controller to execute an authenticated image comprising one of the primary executable code image and the backup image. 2 . The information handling system of claim 1 , wherein the cryptoprocessor is further configured to, responsive to one of the primary executable code image and the backup image failing authentication, prevent the management controller from accessing a memory comprising one of the primary memory and the secondary memory having stored thereon the one of the primary executable code image and the backup image that failed authentication. 3 . The information handling system of claim 1 , wherein the cryptoprocessor is further configured to, responsive to one of the primary executable code image and the backup image failing authentication, communicate an indication to the management controller of such failed authentication. 4 . The information handling system of claim 3 , wherein, responsive to the indication, the management controller is configured to request the cryptoprocessor to allow the management controller to access a memory comprising one of the primary memory and the secondary memory having stored thereon the one of primary executable code image and the backup image that failed authentication, to allow the management controller to recover the one of the primary executable code image and the backup image that failed authentication. 5 . The information handling system of claim 1 , wherein the cryptoprocessor is further configured to, responsive to both of the primary executable code image and the backup image being authenticated, prevent the management controller from accessing the secondary memory during runtime of the management controller in absence of an authenticated sideband request to the secondary memory. 6 . The information handling system of claim 1 , wherein the management controller comprises a baseboard management controller. 7 . The information handling system of claim 1 , wherein the primary executable code image comprises a bootloader of the management controller. 8 . A method comprising, in an information handling system comprising a processor, a management controller communicatively coupled to the processor and configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling system, a primary memory for storing a primary executable code image associated with the management controller, and a secondary memory for storing a backup image to the primary executable code image: upon powering up of the management controller, preventing the management controller from booting from either of the primary executable code image and the backup image; attempting to authenticate the primary executable code image and the backup image; and responsive to at least one of the primary executable code image and the backup image being authenticated, allow the management controller to execute an authenticated image comprising one of the primary executable code image and the backup image. 9 . The method of claim 8 , further comprising, responsive to one of the primary executable code image and the backup image failing authentication, preventing the management controller from accessing a memory comprising one of the primary memory and the secondary memory having stored thereon the one of the primary executable code image and the backup image that failed authentication. 10 . The method of claim 8 , further comprising, responsive to one of the primary executable code image and the backup image failing authentication, communicating an indication to the management controller of such failed authentication. 11 . The method of claim 10 , wherein, responsive to the indication, the management controller is configured to request access to a memory comprising one of the primary memory and the secondary memory having stored thereon the one of the primary executable code image and the backup image that failed authentication, to allow the management controller to recover the one of the primary executable code image and the backup image that failed authentication. 12 . The method of claim 8 , further comprising, responsive to both of the primary executable code image and the backup image being authenticated, preventing the management controller from accessing the secondary memory during runtime of the management controller in absence of an authenticated sideband request to the secondary memory. 13 . The method of claim 8 , wherein the management controller comprises a baseboard management controller. 14 . The method of claim 8 , wherein the primary executable code image comprises a bootloader of the management controller. 15 . A cryptoprocessor comprising processing logic configured to: upon powering up of a management controller communicatively coupled to a processor of an information handling system and configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling system, preventing the management controller from booting; attempt to authenticate a primary executable code image stored in a primary memory and a backup image to the primary executable code image stored in a secondary memory; and responsive to at least one of the primary executable code image and the backup image being authenticated, allow the management controller to execute an authenticated image comprising one of the primary executable code image and the backup image. 16 . The cryptoprocessor of claim 15 , wherein the cryptoprocessor is further configured to, responsive to one of the primary executable code image and the backup image failing authentication, prevent the management controller from accessing a memory comprising one of the primary memory and the secondary memory having stored thereon the one of the primary executable code image and the backup image that failed authentication. 17 . The cryptoprocessor of claim 15 , wherein the cryptoprocessor is further configured to, responsive to one of the primary executable code image and the backup image failing authentication, communicate an indication to the management controller of such failed authentication. 18 . The cryptoprocessor of claim 17 , wherein, responsive to the indication, the management controller is configured to request the cryptoprocessor to allow the management controller to access a memory co

Assignees

Inventors

Classifications

  • where the redundant component is memory or memory area · CPC title

  • Boot up procedures · CPC title

  • to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

  • in cryptographic circuits · CPC title

  • G06F21/575Primary

    Secure boot · CPC title

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Frequently asked questions

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What does patent US2021216640A1 cover?
A cryptoprocessor may comprise processing logic configured to upon powering up of a management controller communicatively coupled to a processor of an information handling system and configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling syst…
Who is the assignee on this patent?
Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification G06F21/575. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 15 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).