Method of manufacturing a semiconductor device and a semiconductor device

Patent metadata

Field	Value
Publication number	US-2021202714-A1
Application number	US-202016945557-A
Country	US
Kind code	A1
Filing date	Jul 31, 2020
Priority date	Dec 30, 2019
Publication date	Jul 1, 2021
Grant date	—

Abstract

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a first dielectric layer over semiconductor fins disposed over a semiconductor substrate; forming a second dielectric layer over the first dielectric layer; recessing the second dielectric layer below a top of each of the semiconductor fins; forming a third dielectric layer over the recessed second dielectric layer; recessing the third dielectric layer below the top of each of the semiconductor fins, thereby forming a wall fin disposed between the semiconductor fins, the wall fin comprising the recessed third dielectric layer and the recessed second dielectric layer disposed under the recessed third dielectric layer; recessing the first dielectric layer below a top of the wall fin; forming a fin liner layer over an upper portion of each of the semiconductor fins and an upper portion of the wall fin, which protrude from the recessed first dielectric layer; etching the fin liner layer and recessing the semiconductor fins; and forming source/drain epitaxial layers over the recessed semiconductor fins, respectively, wherein the source/drain epitaxial layers are separated by the wall fin from each other.

2 . The method of claim 1 , wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are made of different dielectric materials from each other.

3 . The method of claim 2 , wherein the third dielectric layer includes hafnium oxide.

4 . The method of claim 3 , wherein the second dielectric layer includes silicon nitride.

5 . The method of claim 4 , wherein the first dielectric layer includes silicon oxide.

6 . The method of claim 2 , wherein in the etching the fin liner layer, a part of the fin liner layer formed over the upper portion of each of the semiconductor fins remains.

7 . The method of claim 6 , wherein in the etching the fin liner layer, the fin liner formed over the upper portion of the wall fin is fully removed.

8 . The method of claim 6 , wherein the fin liner layer includes silicon nitride.

9 . The method of claim 2 , wherein the source/drain epitaxial layers are in contact with the recessed third dielectric layer of the wall fin.

10 . A method of manufacturing a semiconductor device, the method comprising:
forming a first dielectric layer over a plurality of semiconductor fins disposed over a semiconductor substrate such that a first space remains between adjacent semiconductor fins; forming a second dielectric layer over the first dielectric layer such that the first space is fully filled by the second dielectric layer; recessing the second dielectric layer below a top of each of the plurality of semiconductor fins such that a second space is formed above the recessed second dielectric layer between adjacent semiconductor fins covered by the first dielectric layer; forming a third dielectric layer over the recessed second dielectric layer such that the second space is fully filled by the third dielectric layer; recessing the third dielectric layer below the top of each of the plurality of semiconductor fins, thereby forming wall fins disposed between the adjacent semiconductor fins; recessing the first dielectric layer below a top of each of the wall fins; forming a sacrificial gate structure over an upper portion of each of the plurality of semiconductor fins and an upper portion of each of the wall fins, which protrude from the recessed first dielectric layer; forming a fin liner layer over an upper portion of each of the plurality of semiconductor fins and an upper portion of each of the wall fins, which protrude from the recessed first dielectric layer and are not covered by the sacrificial gate structure; etching the fin liner layer and recessing the plurality of semiconductor fins; forming source/drain epitaxial layers over the plurality of recessed semiconductor fins, respectively; and replacing the sacrificial gate structure with a metal gate structure, wherein the source/drain epitaxial layers are separated by the wall fins from each other.

11 . The method of claim 10 , wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are made of different dielectric materials from each other.

12 . The method of claim 11 , wherein the third dielectric layer includes at least one selected from the group consisting of hafnium oxide, aluminum oxide, zinc oxide and zirconium oxide.

13 . The method of claim 12 , wherein the first dielectric layer includes silicon oxide and the second dielectric layer includes silicon nitride.

14 . The method of claim 10 , wherein in the etching the fin liner layer, a part of the fin liner layer formed over the upper portion of each of the plurality of semiconductor fins remains, and the fin liner formed over the upper portion of each of the wall fins is fully removed.

15 . The method of claim 10 , wherein an interface between the recessed second dielectric layer and the recessed third dielectric layer in each of the wall fins is located above an upper surface of the recessed first dielectric layer.

16 . The method of claim 10 , wherein before the first dielectric layer is formed, a hard mask pattern is formed on the top of each of the plurality of the semiconductor fins.

17 . The method of claim 10 , wherein the first space is fully filled by the second dielectric layer.

18 . A semiconductor device comprising:
a first semiconductor fin and a second semiconductor fin disposed over a semiconductor substrate and extending in a first direction; an isolation insulating layer disposed between the first semiconductor fin and the second semiconductor fin; a wall fin extending in the first direction, wherein a lower portion of the wall fin is embedded in the isolation insulating layer and a upper portion of the wall fin protrudes from the isolation insulating layer; a gate structure disposed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin and extending in a second direction crossing the first direction; and a first source/drain epitaxial layer disposed over a source/drain region of the first semiconductor fin and a second source/drain epitaxial layer disposed over a source/drain region of the second semiconductor fin, wherein: the first source/drain epitaxial layer and the second source/drain epitaxial layer are separated by the wall fin, the wall fin includes a lower dielectric layer and an upper dielectric layer disposed over the lower dielectric layer and made of a different material than the lower dielectric layer, and the upper dielectric layer includes a dielectric material having a dielectric constant higher than the lower dielectric layer and the isolation insulating layer.

19 . The semiconductor device of claim 18 , wherein the upper dielectric layer includes at least one selected from the group consisting of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, and a hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy.

20 . The semiconductor device of claim 18 , wherein the lower dielectric layer includes at least one selected from the group consisting of silicon nitride, silicon oxynitride, SiOC and SiOCN.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chia-Chi
• Hseih Jui Fu
• Lin Yu-Li
• Liao Chih-Teng
• Chen Yi-Jen

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title